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| single-chip 8-bit cmos microcomputer description the 7540 group is the 8-bit microcomputer based on the 740 fam- ily core technology. the 7540 group has a serial i/o, 8-bit timers, a 16-bit timer, and an a-d converter, and is useful for control of home electric appli- ances and office automation equipment. features basic machine-language instructions ...................................... 71 the minimum instruction execution time ......................... 0.34 s (at 6 mhz oscillation frequency, double-speed mode for the shortest instruction) memory size rom ............................................ 8 k to 32 k bytes ram ............................................. 384 to 768 bytes programmable i/o ports ....................... 29 (25 in 32-pin version) interrupts ................................................. 15 sources, 15 vectors ................................. (14 sources, 14 vectors for 32-pin version) timers ............................................................................. 8-bit ? 4 ...................................................................................... 16-bit ? 1 serial i/o1 ................... 8-bit ? 1 (uart or clock-synchronized) serial i/o2 ( note 1 ) ..................... 8-bit ? 1 (clock-synchronized) a-d converter ............................................... 10-bit ? 8 channels .................................................... (6 channels for 32-pin version) clock generating circuit ............................................. built-in type (low-power dissipation by a ring oscillator enabled) (connect to external ceramic resonator or quartz-crystal oscilla- tor permitting rc oscillation) watchdog timer ............................................................ 16-bit ? 1 power source voltage x in oscillation frequency at ceramic oscillation, in double-speed mode at 6 mhz .................................................................... 4.5 to 5.5 v x in oscillation frequency at ceramic oscillation, in high-speed mode at 8 mhz .................................................................... 4.0 to 5.5 v at 4 mhz .................................................................... 2.4 to 5.5 v at 2 mhz .................................................................... 2.2 to 5.5 v x in oscillation frequency at rc oscillation in high-speed mode or middle-speed mode at 4 mhz .................................................................... 4.0 to 5.5 v at 2 mhz .................................................................... 2.4 to 5.5 v at 1 mhz .................................................................... 2.2 to 5.5 v power dissipation mask rom version ....................................... 22.5 mw (standard) one time prom version ................................ 30 mw (standard) operating temperature range ................................... ?0 to 85 ? (?0 to 85 ? for extended operating temperature version) (?0 to 125 ? for extended operating temperature 125 ? ver- sion ( note 2 )) mitsubishi microcomputers 7540 group application office automation equipment, factory automation equipment, home electric appliances, consumer electronics, car, etc. notes 1: serial i/o2 can be used in the following cases; (1) serial i/o1 is not used, (2) serial i/o1 is used as uart and brg output divided by 16 is selected as the synchronized clock. 2: in this version, the operating temperature range and total time are limited as follows; 55 ? to 85 ?: within total 6000 hours, 85 ? to 125 ?: within total 1000 hours.
single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 2 fig. 2 pin configuration (36p2r-a type) packa g e t yp e: 36p2r-a 10 1 2 3 4 6 7 8 9 11 12 14 15 16 5 13 17 18 36 35 34 33 31 30 26 25 24 23 22 21 20 19 32 27 29 28 p0 0 /cntr 1 cnv ss x out x in v ss p0 1 /ty out p0 2 /tz out p0 3 /tx out p0 4 p3 0 (led 0 ) vcc v ref p0 5 p1 0 /r x d 1 p2 6 /an 6 p2 7 /an 7 p1 1 /t x d 1 p1 2 /s clk1 /s clk2 p1 3 /s rdy1 /s data2 p2 3 /an 3 p2 2 /an 2 p2 1 /an 1 p2 0 /an 0 p3 1 (led 1 ) p3 6 (led 6 )/int 1 p2 4 /an 4 p2 5 /an 5 p0 6 p0 7 p3 7 /int 0 reset m37540mx-xxxfp m37540mxt-xxxfp m37540mxv-xxxfp m37540e8fp m37540e8t-xxxfp m37540e8v-xxxfp p1 4 /cntr 0 p3 5 (led 5 ) p3 4 (led 4 ) p3 3 (led 3 ) p3 2 (led 2 ) pin configuration (top view) fig. 1 pin configuration (32p6u-a type) package type: 32p6u-a p0 7 p1 0 /r x d 1 p1 1 /t x d 1 p1 2 /s clk1 /s clk2 p1 3 /s rdy1 /s data2 p1 4 /cntr 0 p2 0 / an 0 p2 1 / an 1 32 31 30 29 28 27 26 25 p3 4 (led 4 ) p3 3 (led 3 ) p3 2 (led 2 ) p3 1 (led 1 ) p3 0 (led 0 ) v ss x out x in 9 10 11 12 13 14 15 16 2 8 7 6 5 3 1 4 v cc cnv ss reset p2 2 /an 2 p0 5 20 17 18 19 21 24 p0 2 /tz out p0 4 p0 3 /tx out p0 6 23 22 p0 1 /ty out p0 0 /cntr 1 p3 7 /int 0 m37540mx-xxxgp m37540mxt-xxxgp m37540mxv-xxxgp m37540exgp m37540e8t-xxxgp m37540e8v-xxxgp p2 3 /an 3 p2 4 /an 4 p2 5 /an 5 v ref single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 3 fig. 4 pin configuration (42s1m type) outline 42s1m 10 1 2 3 4 6 7 8 9 11 12 14 15 16 5 13 17 18 36 35 34 33 31 30 26 25 24 23 22 32 27 29 28 19 20 21 42 41 40 39 37 38 p0 0 /cntr 1 cnv ss x out x in v ss p0 1 /ty out p0 2 /tz out p0 3 /tx out p0 4 p3 0 (led 0 ) vcc v ref p0 5 p1 2 /s clk1 /s clk2 p2 5 /an 5 p2 6 /an 6 p1 3 /s rdy1 /s data2 p1 4 /cntr 0 nc p2 2 /an 2 nc p2 1 /an 1 p2 0 /an 0 p3 1 (led 1 ) p3 6 (led 6 )/int 1 p2 3 /an 3 p2 4 /an 4 p0 6 p0 7 p3 7 /int 0 reset m37540rss nc p3 5 (led 5 ) p3 4 (led 4 ) p3 3 (led 3 ) p3 2 (led 2 ) nc p1 0 /r x d 1 p1 1 /t x d 1 nc nc p2 7 /an 7 fig. 3 pin configuration (32p4b-a type) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 cnv ss p1 2 /s clk1 /s clk2 p1 3 /s rdy1 /s data2 p1 4 /cntr 0 p2 0 /an 0 p2 1 /an 1 p2 2 /an 2 p2 3 /an 3 p2 4 /an 4 v cc x in x out v ss p1 1 /t x d 1 p1 0 /r x d 1 p0 7 p0 6 p0 5 p0 4 p3 0 (led 0 ) p2 5 /an 5 v ref reset p0 0 /cntr 1 p3 3 (led 3 ) p3 2 (led 2 ) p3 1 (led 1 ) m37540mx-xxxsp m37540exsp 32 p0 1 /ty out p0 2 /tz out p0 3 /tx out 14 15 16 p3 7 /int 0 p3 4 (led 4 ) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 package type: 32p4b single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 4 functional block fig. 5 functional block diagram (32p6u package) functional block diagram (package: 32p6u) x in out x si/o1(8) ram rom cpu a x y s pc h pc l ps v ss 11 reset 6 v cc 8 7 cnv ss p1(5) 30 28 26 29 27 32 31 p2(6) p3(6) 12 15 13 5 reset input i/o port p2 i/o port p1 i/o port p3 clock generating circuit clock input clock output 9 10 4 2 3 1 a-d converter (10) v ref watchdog timer reset 0 14 int 0 16 17 si/o2(8) cntr 0 i/o port p0 prescaler y (8) prescaler z (8) timer x (8) timer z (8) timer y (8) key-on wakeup ty out tz out prescaler x (8) cntr 1 timer a (16) p0(8) 25 23 21 19 24 22 20 18 int 0 timer 1 (8) prescaler 1 (8) tx out single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 5 fig. 6 functional block diagram (36p2r package) functional block diagram (package: 36p2r) a-d converter (10) x in out x cpu v ss 18 reset 13 v cc 15 14 cnv ss p0(8) 34 32 30 28 33 31 29 27 p1(5) 31 35 2 36 7 5 6 4 p2(8) p3(8) 20 23 21 19 12 i/o port p2 i/o port p0 i/o port p1 i/o port p3 16 17 11 9 10 8 0 22 26 24 25 si/o1(8) ram rom a x y s pc h pc l ps reset input clock generating circuit clock input clock output v ref watchdog timer reset int 0 si/o2(8) cntr 0 prescaler y (8) prescaler z (8) timer x (8) timer z (8) timer y (8) key-on wakeup ty out tz out prescaler x (8) cntr 1 timer a (16) int 0 timer 1 (8) prescaler 1 (8) tx out int 1 single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 6 fig. 7 functional block diagram (32p4b package) functional block diagram (package: 32p4b) 16 11 13 12 p1(5) 31 31 2 32 5 4 p2(6) p3(6) 17 20 18 10 14 15 9 7 8 6 0 19 21 22 p0(8) 30 28 26 24 29 27 25 23 a-d converter (10) x in out x cpu v ss reset v cc cnv ss i/o port p2 i/o port p0 i/o port p1 i/o port p3 si/o1(8) ram rom a x y s pc h pc l ps reset input clock generating circuit clock input clock output v ref watchdog timer reset int 0 si/o2(8) cntr 0 prescaler y (8) prescaler z (8) timer x (8) timer z (8) timer y (8) key-on wakeup ty out tz out prescaler x (8) cntr 1 timer a (16) int 0 timer 1 (8) prescaler 1 (8) tx out single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 7 pin description table 1 pin description function apply voltage of 2.2 to 5.5 v to vcc, and 0 v to vss. reference voltage input pin for a-d converter chip operating mode control pin, which is always connected to vss. reset input pin for active l input and output pins for main clock generating circuit connect a ceramic resonator or quartz crystal oscillator between the x in and x out pins. for using rc oscillator, short between the x in and x out pins, and connect the capacitor and resistor. if an external clock is used, connect the clock source to the x in pin and leave the x out pin open. when the ring oscillator is selected as the main clock, connect x in pin to v ss and leave x out open. function expect a port function name power source (note 1) analog reference voltage cnvss reset input clock input i/o port p0 i/o port p1 pin vcc, vss v ref cnvss reset x in p0 0 /cntr 1 p0 1 /ty out p0 2 /tz out p0 3 /tx out p0 4 p0 7 notes 1: v cc = 2.4 to 5.5 v for the extended operating temperature version and the extended operating temperature 125 c version. 2: p2 6 /an 6 and p2 7 /an 7 do not exist for the 32-pin version, so that port p2 is a 6-bit i/o port. 3: p3 5 and p3 6 /int 1 do not exist for the 32-pin version, so that port p3 is a 6-bit i/o port. key-input (key-on wake up interrupt input) pins timer y, timer z, timer x and timer a function pin 8-bit i/o port. i/o direction register allows each pin to be individually pro- grammed as either input or output. cmos compatible input level cmos 3-state output structure whether a built-in pull-up resistor is to be used or not can be de- termined by program. 5-bit i/o port i/o direction register allows each pin to be individually pro- grammed as either input or output. cmos compatible input level cmos 3-state output structure cmos/ttl level can be switched for p1 0 , p1 2 and p1 3 8-bit i/o port having almost the same function as p0 cmos compatible input level cmos 3-state output structure 8-bit i/o port p1 0 /rxd 1 p1 1 /txd 1 p1 2 /s clk1 /s clk2 p1 3 /s rdy1 /s data2 p1 4 /cntr 0 p2 0 /an 0 p2 7 /an 7 p3 0 p3 5 p3 6 /int 1 p3 7 /int 0 i/o port p2 (note 2) i/o port p3 (note 3) serial i/o1 function pin serial i/o1 function pin serial i/o2 function pin timer x function pin input pins for a-d converter interrupt input pins i/o direction register allows each pin to be individually programmed as either input or output. cmos compatible input level (cmos/ttl level can be switched for p3 6 and p3 7 ). cmos 3-state output structure p3 0 to p3 6 can output a large current for driving led. x out clock output whether a built-in pull-up resistor is to be used or not can be de- termined by program. single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 8 group expansion mitsubishi plans to expand the 7540 group as follow: memory type support for mask rom version, one time prom version, and emulator mcu . memory size rom/prom size ................................................. 8 k to 32 k bytes ram size .............................................................. 384 to 768 bytes package 32p4b .................................................. 32-pin plastic molded sdip 32p6u-a ...................... 0.8 mm-pitch 32-pin plastic molded lqfp 36p2r-a ...................... 0.8 mm-pitch 36-pin plastic molded ssop 42s1m .................................... 42-pin shrink ceramic piggy back fig. 8 memory expansion plan 3 8 4 3 2 k r o m s i z e ( b y t e s ) r a m s i z e ( b y t e s ) 5 1 27 6 8 16 k 0 u n d e r d e v e l o p m e n t m 3 7 5 4 0 e 8 m37540m4 m37540m4t n o t e : p r o d u c t s u n d e r d e v e l o p m e n t t h e d e v e l o p m e n t s c h e d u l e a n d s p e c i f i c a t i o n m a y b e r e v i s e d w i t h o u t n o t i c e . 8k m 3 7 5 4 0 e 8 t m 3 7 5 4 0 e 8 v u n d e r d e v e l o p m e n t m 3 7 5 4 0 m 2 t m 3 7 5 4 0 m 2 m37540e2 u n d e r d e v e l o p m e n t m37540m2v m37540m4v single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 9 currently supported products are listed below. table 2 list of supported products product (p) rom size (bytes) rom size for user () 8192 (8062) 16384 (16254) 8192 (8062) 32768 (32638) ram size (bytes) 384 512 384 768 768 package 32p4b 36p2r-a 32p6u-a 32p4b 36p2r-a 32p6u-a 32p4b 36p2r-a 32p6u-a 32p4b 36p2r-a 32p6u-a 42s1m remarks mask rom version mask rom version mask rom version (extended operating temperature version) mask rom version (extended operating temperature 125 c version) mask rom version mask rom version (extended operating temperature version) mask rom version (extended operating temperature 125 c version) mask rom version mask rom version mask rom version (extended operating temperature version) mask rom version (extended operating temperature 125 c version) mask rom version mask rom version (extended operating temperature version) mask rom version (extended operating temperature 125 c version) one time prom version (blank) one time prom version (blank) one time prom version (blank) one time prom version (blank) one time prom version (blank) one time prom version (shipped after programming, extended operating temperature version) one time prom version (shipped after programming, extended operating temperature 125 c version) one time prom version (blank) one time prom version (shipped after programming, extended operating temperature version) one time prom version (shipped after programming, extended operating temperature 125 c version) emulator mcu m37540m2-xxxsp m37540m2-xxxfp m37540m2t-xxxfp m37540m2v-xxxfp m37540m2-xxxgp m37540m2t-xxxgp m37540m2v-xxxgp m37540m4-xxxsp M37540M4-XXXFP m37540m4t-xxxfp m37540m4v-xxxfp m37540m4-xxxgp m37540m4t-xxxgp m37540m4v-xxxgp m37540e2sp* m37540e2fp* m37540e2gp* m37540e8sp m37540e8fp m37540e8t-xxxfp* m37540e8v-xxxfp* m37540e8gp m37540e8t-xxxgp* m37540e8v-xxxgp* m37540rss *: under development single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 10 b7 b0 x b7 b0 s b7 b0 y b7 b0 pc l processor status register (ps) carry flag b7 b0 b7 b0 a b15 pc h zero flag interrupt disable flag decimal mode flag break flag index x mode flag overflow flag negative flag program counter stack pointer index register y index register x accumulator c z i d b t v n functional description central processing unit (cpu) the mcu uses the standard 740 family instruction set. refer to the table of 740 family addressing modes and machine-language instructions or the series 740 single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 11 execute jsr on-going routine m (s) (pc h ) (s) (s 1) m (s) (pc l ) execute rts (pc l ) m (s) (s) (s 1) (s) (s + 1) (s) (s + 1) (pc h ) m (s) subroutine restore return address store return address on stack m (s) (ps) execute rti (ps) m (s) (s) (s 1) (s) (s + 1) interrupt service routine restore contents of processor status register m (s) (pc h ) (s) (s 1) m (s) (pc l ) (s) (s 1) (pc l ) m (s) (s) (s + 1) (s) (s + 1) (pc h ) m (s) restore return address i flag 0 to 1 fetch the jump vector store return address on stack store contents of processor status register on stack interrupt request (note) note : the condition to enable the interrupt interrupt enable bit is 1 interrupt disable flag is 0 table 3 push and pop instructions of accumulator or processor status register accumulator processor status register push instruction to stack pha php pop instruction from stack pla plp fig. 10 register push and pop at interrupt generation and subroutine call single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 12 processor status register (ps) the processor status register is an 8-bit register consisting of flags which indicate the status of the processor after an arithmetic operation. branch operations can be performed by testing the carry (c) flag, zero (z) flag, overflow (v) flag, or the negative (n) flag. in decimal mode, the z, v, n flags are not valid. after reset, the interrupt disable (i) flag is set to 1 , but all other flags are undefined. since the index x mode (t) and decimal mode (d) flags directly affect arithmetic operations, they should be initialized in the beginning of a program. (1) carry flag (c) the c flag contains a carry or borrow generated by the arithmetic logic unit (alu) immediately after an arithmetic operation. it can also be changed by a shift or rotate instruction. (2) zero flag (z) the z flag is set if the result of an immediate arithmetic operation or a data transfer is 0 , and cleared if the result is anything other than 0 . (3) interrupt disable flag (i) the i flag disables all interrupts except for the interrupt generated by the brk instruction. interrupts are disabled when the i flag is 1 . when an interrupt occurs, this flag is automatically set to 1 to prevent other interrupts from interfering until the current interrupt is serviced. (4) decimal mode flag (d) the d flag determines whether additions and subtractions are ex- ecuted in binary or decimal. binary arithmetic is executed when this flag is 0 ; decimal arithmetic is executed when it is 1 . decimal correction is automatic in decimal mode. only the adc and sbc instructions can be used for decimal arithmetic. (5) break flag (b) the b flag is used to indicate that the current interrupt was gener- ated by the brk instruction. the brk flag in the processor status register is always 0 . when the brk instruction is used to gener- ate an interrupt, the processor status register is pushed onto the stack with the break flag set to 1 . the saved processor status is the only place where the break flag is ever set. (6) index x mode flag (t) when the t flag is 0 , arithmetic operations are performed be- tween accumulator and memory, e.g. the results of an operation between two memory locations is stored in the accumulator. when the t flag is 1 , direct arithmetic operations and direct data trans- fers are enabled between memory locations, i.e. between memory and memory, memory and i/o, and i/o and i/o. in this case, the result of an arithmetic operation performed on data in memory lo- cation 1 and memory location 2 is stored in memory location 1. the address of memory location 1 is specified by index register x, and the address of memory location 2 is specified by normal ad- dressing modes. (7) overflow flag (v) the v flag is used during the addition or subtraction of one byte of signed data. it is set if the result exceeds +127 to -128. when the bit instruction is executed, bit 6 of the memory location oper- ated on by the bit instruction is stored in the overflow flag. (8) negative flag (n) the n flag is set if the result of an arithmetic operation or data transfer is negative. when the bit instruction is executed, bit 7 of the memory location operated on by the bit instruction is stored in the negative flag. table 4 set and clear instructions of each bit of processor status register set instruction clear instruction c flag sec clc z flag i flag sei cli d flag sed cld b flag t flag set clt v flag clv n flag single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 13 [cpu mode register] cpum the cpu mode register contains the stack page selection bit. this register is allocated at address 003b16. switching method of cpu mode register switch the cpu mode register (cpum) at the head of program af- ter releasing reset in the following method. fig. 12 switching method of cpu mode register fig. 11 structure of cpu mode register oscillation mode selection bit (note 1) 0 : ceramic oscillation 1 : rc oscillation cpu mode register (cpum: address 003b 16 , initial value: 80 16 ) stack page selection bit 0 : 0 page 1 : 1 page clock division ratio selection bits b7 b6 0 0 : f( ) = f(x in )/2 (high-speed mode) 0 1 : f( ) = f(x in )/8 (middle-speed mode) 1 0 : applied from ring oscillator 1 1 : f( ) = f(x in ) (double-speed mode)(note 2) ring oscillator oscillation control bit 0 : ring oscillator oscillation enabled 1 : ring oscillator oscillation stop x in oscillation control bit 0 : ceramic or rc oscillation enabled 1 : ceramic or rc oscillation stop processor mode bits (note 1) b1 b0 0 0 single-chip mode 0 1 1 0 1 1 not available b7 b0 2: these bits are used only when a ceramic oscillation is selected. note 1: the bit can be rewritten only once after releasing reset. after rewriting it is disable to write any data to the bit. however, by reset the bit is initialized and can be rewritten, again. (it is not disable to write any data to the bit for emulator mcu m37540rss .) do not use these when an rc oscillation is selected. after releasing reset switch the oscillation mode selection bit (bit 5 of cpum) switch the clock division ratio selection bits (bits 6 and 7 of cpum) main routine start with a built-in ring oscillator an initial value is set as a ceramic oscillation mode. when it is switched to an rc oscillation, its oscillation starts. select 1/1, 1/2, 1/8 or ring oscillator. wait by ring oscillator operation until establishment of oscillator clock when using a ceramic oscillation, wait until establlishment of oscillation from oscillation starts. when using an rc oscillation, wait time is not required basically (time to execute the instruction to switch from a ring oscillator meets the requirement). single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 14 memory special function register (sfr) area the sfr area in the zero page contains control registers such as i/o ports and timers. ram ram is used for data storage and for a stack area of subroutine calls and interrupts. rom the first 128 bytes and the last 2 bytes of rom are reserved for device testing and the rest is a user area for storing programs. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page the 256 bytes from addresses 0000 16 to 00ff 16 are called the zero page area. the internal ram and the special function regis- ters (sfr) are allocated to this area. the zero page addressing mode can be used to specify memory and register addresses in the zero page area. access to this area with only 2 bytes is possible in the zero page addressing mode. special page the 256 bytes from addresses ff00 16 to ffff 16 are called the special page area. the special page addressing mode can be used to specify memory addresses in the special page area. ac- cess to this area with only 2 bytes is possible in the special page addressing mode. fig. 13 memory map diagram 0100 16 0000 16 0040 16 0440 1 6 ff00 16 ffdc 1 6 fffe 16 ffff 16 3 8 4 5 1 2 7 6 8 xxxx 16 0 1 b f 1 6 0 2 3 f 1 6 0 3 3 f 1 6 8 1 9 2 1 6 3 8 4 3 2 7 6 8 e000 16 c000 16 8000 16 e 0 8 0 1 6 c 0 8 0 1 6 8 0 8 0 1 6 y y y y 1 6 zzzz 16 ram rom r e s e r v e d a r e a s f r a r e a not used i n t e r r u p t v e c t o r a r e a r o m a r e a reserved rom area (128 bytes) z e r o p a g e special page r a m a r e a r a m c a p a c i t y ( b y t e s ) address xxxx 16 r o m c a p a c i t y ( b y t e s ) a d d r e s s y y y y 1 6 reserved rom area a d d r e s s z z z z 1 6 single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 15 fig. 14 memory map of special function register (sfr) note : do not access to the sfr area including nothing. 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p3 direction register (p3d) pull-up control register (pull) transmit/receive buffer register (tb/rb) serial i/o1 status register (sio1sts) serial i/o1 control register (sio1con) uart control register (uartcon) baud rate generator (brg) port p1p3 control register (p1p3c) 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 timer count source set register (tcss) a-d conversion register (low-order) (adl) prescaler 1 (pre1) timer 1 (t1) one-shot start register (ons) timer x mode register (txm) prescaler x (prex) timer x (tx) serial i/o2 control register (sio2con) serial i/o2 register (sio2) a-d control register (adcon) a-d conversion register (high-order) (adh) misrg watchdog timer control register (wdtcon) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1 (ireq1) interrupt control register 1 (icon1) timer a mode register (tam) timer a (low-order) (tal) timer a (high-order) (tah) timer y, z mode register (tyzm) prescaler y (prey) timer y secondary (tys) timer y primary (typ) timer y, z waveform output control register (pum) prescaler z (prez) timer z secondary (tzs) timer z primary (tzp) interrupt request register 2 (ireq2) interrupt control register 2 (icon2) single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 16 i/o ports [direction registers] pid the i/o ports have direction registers which determine the input/ output direction of each pin. each bit in a direction register corre- sponds to one pin, and each pin can be set to be input or output. when 1 is set to the bit corresponding to a pin, this pin becomes an output port. when 0 is set to the bit, the pin becomes an in- put port. when data is read from a pin set to output, not the value of the pin itself but the value of port latch is read. pins set to input are float- ing, and permit reading pin values. if a pin set to input is written to, only the port latch is written to and the pin remains floating. [pull-up control register] pull by setting the pull-up control register (address 0016 16 ), ports p0 and p3 can exert pull-up control by program. however, pins set to output are disconnected from this control and cannot exert pull-up control. [port p1p3 control register] p1p3c by setting the port p1p3 control register (address 0017 16 ), a cmos input level or a ttl input level can be selected for ports p1 0 , p1 2 , p1 3 , p3 6 , and p3 7 by program. fig. 16 structure of port p1p3 control register fig. 15 structure of pull-up control register port p1p3 control register (p1p3c: address 0017 16 , initial value: 00 16 ) b7 b0 p3 7 /int 0 input level selection bit 0 : cmos level 1 : ttl level p3 6 /int 1 input level selection bit 0 : cmos level 1 : ttl level p1 0 ,p1 2 ,p1 3 input level selection bit 0 : cmos level 1 : ttl level not used note: keep setting the p3 6 /int 1 input level selection bit to 0 (initial value) for 32-pin version. pull-up control register (pull: address 0016 16 , initial value: 00 16 ) p0 0 pull-up control bit p0 1 pull-up control bit p0 2 , p0 3 pull-up control bit p0 4 p0 7 pull-up control bit p3 0 p3 3 pull-up control bit p3 4 pull-up control bit p3 5 , p3 6 pull-up control bit p3 7 pull-up control bit b7 b0 0 : pull-up off 1 : pull-up on note 1: pins set to output ports are disconnected from pull-up control. 2: set the p3 5 , p3 6 pull-up control bit to 1 (initial value: 0 ) for 32-pin version. single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 17 table 5 i/o port function table pin p0 0 /cntr 1 p0 1 /ty out p0 2 /tz out p0 3 /tx out p0 4 p0 7 p1 0 /rxd 1 p1 1 /txd 1 p1 2 /s clk1 /s clk2 p1 3 /s rdy1 /s data2 p1 4 /cntr 0 p2 0 /an 0 p2 7 /an 7 p3 0 p3 5 p3 6 /int 1 p3 7 /int 0 input/output i/o individual bits i/o format cmos compatible input level cmos 3-state output (note 1) non-port function key input interrupt timer x function output timer y function output timer z function output timer a function input serial i/o1 function input/output serial i/o2 function input/output timer x function input/output a-d conversion input external interrupt input related sfrs pull-up control register timer y mode register timer z mode register timer x mode register timer y,z waveform output control register timer a mode register serial i/o1 control register serial i/o1 control register serial i/o2 control register timer x mode register a-d control register interrupt edge selection register diagram no. (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) notes 1: ports p1 0 , p1 2 , p1 3 , p3 6 , and p3 7 are cmos/ttl level. 2: p2 6/ an 6 and p2 7 /an 7 do not exist for the 32-pin version. 3: p3 5 and p3 6 /int 1 do not exist for the 32-pin version. name i/o port p0 i/o port p1 i/o port p2 (note 2) i/o port p3 (note 3) single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 18 fig. 17 block diagram of ports (1) (6)port p1 1 data bus port latch serial i/o1 output p1 1 /t x d 1 p-channel output disable bit (5)port p1 0 (4)ports p0 4 p0 7 (1)port p0 0 direction register data bus port latch pull-up control to key input interrupt generating circuit cntr 1 interrupt input (2)ports p0 1, p0 2 pulse output mode timer output (7)port p1 2 serial i/o1, serial i/o2 clock output serial i/o1 mode selection bit serial i/o1 enable bit serial i/o1 enable bit serial i/o1 synchronous clock selection bit s clk2 pin selection bit (3)port p0 3 direction register data bus port latch pull-up control to key input interrupt generating circuit direction register data bus port latch pull-up control to key input interrupt generating circuit timer output p0 3 /tx out output valid direction register data bus port latch pull-up control to key input interrupt generating circuit direction register data bus port latch serial i/o1 enable bit receive enable bit serial i/o1 input p1 0 , p1 2 , p1 3 input level selection bit direction register serial i/o1 enable bit transmit enable bit direction register data bus port latch serial i/o1, serial i/o2 clock input p1 0 , p1 2 , p1 3 input level selection bit * * * p1 0 , p1 2 , p1 3 , p3 6 , and p3 7 input level are switched to the cmos/ttl level by the port p1p3 control register. p0 0 key-on wakeup selection bit when the ttl level is selected, there is no hysteresis characteristics. single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 19 fig. 18 block diagram of ports (2) pull-up control int interrupt input p3 input level selection bit (11) ports p3 0 p3 5 pull-up control (9) port p1 4 data bus serial i/o1 ready output serial i/o2 output serial i/o2 input s data2 pin selection bit port latch direction register s data2 output in operation signal cntr 0 interrupt input pulse output mode timer output p1 0 , p1 2 , p1 3 input level selection bit serial i/o mode selection bit serial i/o1 enable bit s rdy1 output enable bit p1 0 , p1 2 , p1 3 , p3 6 , and p3 7 input level are switched to the cmos/ttl level by the port p1p3 control register. data bus port latch direction register data bus port latch direction register data bus port latch direction register a-d converter input analog input pin selection bit (12) ports p3 6 , p3 7 data bus port latch direction register * * (10) ports p2 0 p2 7 * (8) port p1 3 when the ttl level is selected , there is no h y steresis characteristics. single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 20 interrupts interrupts occur by 15 different sources : 5 external sources, 9 in- ternal sources and 1 software source. interrupt control all interrupts except the brk instruction interrupt have an interrupt request bit and an interrupt enable bit, and they are controlled by the interrupt disable flag. when the interrupt enable bit and the in- terrupt request bit are set to 1 and the interrupt disable flag is set to 0 , an interrupt is accepted. the interrupt request bit can be cleared by program but not be set. the interrupt enable bit can be set and cleared by program. the reset and brk instruction interrupt can never be disabled with any flag or bit. all interrupts except these are disabled when the interrupt disable flag is set. when several interrupts occur at the same time, the interrupts are received according to priority. interrupt operation upon acceptance of an interrupt the following operations are auto- matically performed: 1. the processing being executed is stopped. 2. the contents of the program counter and processor status reg- ister are automatically pushed onto the stack. 3. the interrupt disable flag is set and the corresponding interrupt request bit is cleared. 4. concurrently with the push operation, the interrupt destination address is read from the vector table into the program counter. notes on use when setting the followings, the interrupt request bit may be set to 1 . when setting external interrupt active edge related register: interrupt edge selection register (address 003a16) timer x mode register (address 2b 16 ) timer a mode register (address 1d 16 ) when not requiring the interrupt occurrence synchronized with these setting, take the following sequence. ? set the corresponding interrupt enable bit to 0 (disabled). ? set the interrupt edge select bit (active edge switch bit) to 1 . ? set the corresponding interrupt request bit to 0 after 1 or more instructions have been executed. ? set the corresponding interrupt enable bit to 1 (enabled). table 6 interrupt vector address and priority vector addresses (note 1) high-order priority low-order interrupt request generating conditions remarks interrupt source fffc 16 fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16 fffd 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 note 1: vector addressed contain internal jump destination addresses. 2: reset function in the same way as an interrupt with the highest priority. 3: it is an interrupt which can use only for 36 pin version. non-maskable valid only when serial i/o1 is selected valid only when serial i/o1 is selected external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (valid at falling) external interrupt (active edge selectable) external interrupt (active edge selectable) stp release timer underflow non-maskable software interrupt at reset input at completion of serial i/o1 data receive at completion of serial i/o1 transmit shift or when transmit buffer is empty at detection of either rising or falling edge of int 0 input at detection of either rising or falling edge of int 1 input at falling of conjunction of input logical level for port p0 (at input) at detection of either rising or falling edge of cntr 0 input at detection of either rising or falling edge of cntr 1 input at timer x underflow at timer y underflow at timer z underflow at timer a underflow at completion of transmit/receive shift at completion of a-d conversion at timer 1 underflow not available at brk instruction execution 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 reset (note 2) serial i/o1 receive serial i/o1 transmit int 0 int 1 (note 3) key-on wake-up cntr 0 cntr 1 timer x timer y timer z timer a serial i/o2 a-d conversion timer 1 reserved area brk instruction single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 21 fig. 19 interrupt control fig. 20 structure of interrupt-related registers interrupt disable flag i interrupt request interrupt request bit interrupt enable bit brk instruction reset b7 b0 b7 b0 b7 b0 interrupt edge selection register int 0 interrupt edge selection bit 0 : falling edge active 1 : rising edge active int 1 interrupt edge selection bit 0 : falling edge active 1 : rising edge active not used (returns 0 when read) p0 0 key-on wakeup enable bit 0 : key-on wakeup enabled 1 : key-on wakeup disabled (intedge : address 003a 16 , initial value : 00 16 ) interrupt request register 1 serial i/o1 receive interrupt request bit serial i/o1 transmit interrupt request bit int 0 interrupt request bit int 1 interrupt request bit key-on wake up interrupt request bit cntr 0 interrupt request bit cntr 1 interrupt request bit timer x interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued (ireq1 : address 003c 16 , initial value : 00 16 ) b7 b0 interrupt control register 1 serial i/o1 receive interrupt enable bit serial i/o1 transmit interrupt enable bit int 0 interrupt enable bit int 1 interrupt enable bit (do not write 1 to this bit for 32-pin version) key-on wake up interrupt enable bit cntr 0 interrupt enable bit cntr 1 interrupt enable bit timer x interrupt enable bit 0 : interrupts disabled 1 : interrupts enabled (icon1 : address 003e 16 , initial value : 00 16 ) interrupt request register 2 timer y interrupt request bit timer z interrupt request bit timer a interrupt request bit serial i/o2 interrupt request bit a-d conversion interrupt request bit timer 1 interrupt request bit not used (returns 0 when read) 0 : no interrupt request issued 1 : interrupt request issued (ireq2 : address 003d 16 , initial value : 00 16 ) b7 b0 interrupt control register 2 timer y interrupt enable bit timer z interrupt enable bit timer a interrupt enable bit serial i/o2 interrupt enable bit a-d conversion interrupt enable bit timer 1 interrupt enable bit not used (returns 0 when read) (do not write 1 to this bit) 0 : interrupts disabled 1 : interrupts enabled (icon2 : address 003f 16 , initial value : 00 16 ) single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 22 key input interrupt (key-on wake-up) a key-on wake-up interrupt request is generated by applying l level to any pin of port p0 that has been set to input mode. in other words, it is generated when the and of input level goes from 1 to 0 . an example of using a key input interrupt is shown in figure 21, where an interrupt request is generated by pressing one of the keys provided as an active-low key matrix which uses ports p0 0 to p0 3 as input ports. fig. 21 connection example when using key input interrupt and port p0 block diagram port pxx l level output pull register bit 3 = 0 port p0 7 latch port p0 7 direction register = 1 ** * p0 7 output key input interrupt request port p0 input read circuit * p-channel transistor for pull-up ** cmos output buffer pull register bit 3 = 0 port p0 6 latch port p0 6 direction register = 1 ** * p0 6 output pull register bit 3 = 0 port p0 5 latch port p0 5 direction register = 1 ** * p0 5 output pull register bit 3 = 0 port p0 4 latch port p0 4 direction register = 1 ** * p0 4 output pull register bit 2 = 1 port p0 3 latch port p0 3 direction register = 0 ** * p0 3 input pull register bit 2 = 1 port p0 2 latch port p0 2 direction register = 0 ** * p0 2 input pull register bit 1 = 1 port p0 1 latch port p0 1 direction register = 0 ** * p0 1 input pull register bit 0 = 1 port p0 0 latch port p0 0 direction register = 0 ** * p0 0 input falling edge detection falling edge detection falling edge detection falling edge detection falling edge detection falling edge detection falling edge detection falling edge detection port p0 0 key-on wakeup selection bit single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 23 timers the 7540 group has 5 timers: timer 1, timer a, timer x, timer y and timer z. the division ratio of every timer and prescaler is 1/(n+1) provided that the value of the timer latch or prescaler is n. all the timers are down count timers. when a timer reaches 0 , an underflow occurs at the next count pulse, and the corresponding timer latch is reloaded into the timer. when a timer underflows, the interrupt request bit corresponding to each timer is set to 1 . timer 1 timer 1 is an 8-bit timer and counts the prescaler output. when timer 1 underflows, the timer 1 interrupt request bit is set to 1 . prescaler 1 is an 8-bit prescaler and counts the signal which is the oscillation frequency divided by 16. prescaler 1 and timer 1 have the prescaler 1 latch and the timer 1 latch to retain the reload value, respectively. the value of prescaler 1 latch is set to prescaler 1 when prescaler 1 underflows.the value of timer 1 latch is set to timer 1 when timer 1 underflows. when writing to prescaler 1 (pre1) is executed, the value is writ- ten to both the prescaler 1 latch and prescaler 1. when writing to timer 1 (t1) is executed, the value is written to both the timer 1 latch and timer 1. when reading from prescaler 1 (pre1) and timer 1 (t1) is ex- ecuted, each count value is read out. timer 1 always operates in the timer mode. prescaler 1 counts the signal which is the oscillation frequency di- vided by 16. each time the count clock is input, the contents of prescaler 1 is decremented by 1. when the contents of prescaler 1 reach 00 16 , an underflow occurs at the next count clock, and the prescaler 1 latch is reloaded into prescaler 1 and count contin- ues. the division ratio of prescaler 1 is 1/(n+1) provided that the value of prescaler 1 is n. the contents of timer 1 is decremented by 1 each time the under- flow signal of prescaler 1 is input. when the contents of timer 1 reach 00 16 , an underflow occurs at the next count clock, and the timer 1 latch is reloaded into timer 1 and count continues. the di- vision ratio of timer 1 is 1/(m+1) provided that the value of timer 1 is m. accordingly, the division ratio of prescaler 1 and timer 1 is 1/((n+1) ? (m+1)) provided that the value of prescaler 1 is n and the value of timer 1 is m. timer 1 cannot stop counting by software. timer a timer a is a 16-bit timer and counts the signal which is the oscil- lation frequency divided by 16. when timer a underflows, the timer a interrupt request bit is set to 1 . timer a consists of the low-order of timer a (tal) and the high-or- der of timer a (tah). timer a has the timer a latch to retain the reload value. the value of timer a latch is set to timer a at the timing shown below. when timer a undeflows. when an active edge is input from cntr 1 pin (valid only when period measurement mode and pulse width hl continuously mea- surement mode). when writing to both the low-order of timer a (tal) and the high- order of timer a (tah) is executed, the value is written to both the timer a latch and timer a. when reading from the low-order of timer a (tal) and the high-or- der of timer a (tah) is executed, the following values are read out according to the operating mode. in timer mode, event counter mode: the count value of timer a is read out. in period measurement mode, pulse width hl continuously mea- surement mode: the measured value is read out. be sure to write to/read out the low-order of timer a (tal) and the high-order of timer a (tah) in the following order; read read the high-order of timer a (tah) first, and the low-order of timer a (tal) next and be sure to read out both tah and tal. write write to the low-order of timer a (tal) first, and the high-order of timer a (tah) next and be sure to write to both tal and tah. timer a can be selected in one of 4 operating modes by setting the timer a mode register. (1) timer mode timer a counts the oscillation frequency divided by 16. each time the count clock is input, the contents of timer a is decremented by 1. when the contents of timer a reach 0000 16 , an underflow oc- curs at the next count clock, and the timer a latch is reloaded into timer a. the division ratio of timer a is 1/(n+1) provided that the value of timer a is n. (2) period measurement mode in the period measurement mode, the pulse period input from the p0 0 /cntr 1 pin is measured. cntr 1 interrupt request is generated at rising/falling edge of cntr 1 pin input singal. simultaneousuly, the value in the timer a latch is reloaded intimer a and count continues. the active edge of cntr 1 pin input signal can be selected from rising or falling by the cntr 1 active edge switch bit .the count value when trigger input from cntr 1 pin is accepted is retained until timer a is read once. single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 24 (3) event counter mode timer a counts signals input from the p0 0 /cntr 1 pin. except for this, the operation in event counter mode is the same as in timer mode. the active edge of cntr 1 pin input signal can be selected from rising or falling by the cntr 1 active edge switch bit . (4) pulse width hl continuously measurement mode in the pulse width hl continuously measurement mode, the pulse width ( h and l levels) input to the p0 0 /cntr 1 pin is measured. cntr 1 interrupt request is generated at both rising and falling edges of cntr 1 pin input signal. except for this, the operation in pulse width hl continuously measurement mode is the same as in period measurement mode. the count value when trigger input from the cntr 1 pin is ac- cepted is retained until timer a is read once. timer a can stop counting by setting 1 to the timer a count stop bit in any mode. also, when timer a underflows, the timer a interrupt request bit is set to 1 . note on timer a is described below; note on timer a cntr 1 interrupt active edge selection cntr 1 interrupt active edge depends on the cntr 1 active edge switch bit. when this bit is 0 , the cntr 1 interrupt request bit is set to 1 at the falling edge of the cntr 1 pin input signal. when this bit is 1 , the cntr 1 interrupt request bit is set to 1 at the rising edge of the cntr 1 pin input signal. however, in the pulse width hl continuously measurement mode, cntr 1 interrupt request is generated at both rising and falling edges of cntr 1 pin input signal regardless of the setting of cntr 1 active edge switch bit. fig. 22 structure of timer a mode register timer a mode register (tam : address 001d 16 , initial value: 00 16 ) b7 b0 not used (return 0 when read) timer a operating mode bits b5 b4 0 0 : timer mode 0 1 : period measurement mode 1 0 : event counter mode 1 1 : pulse width hl continuously measurement mode cntr 1 active edge switch bit 0 : count at rising edge in event counter mode measure the falling edge period in period measurement mode falling edge active for cntr 1 interrupt 1 : count at falling edge in event counter mode measure the rising edge period in period measurement mode rising edge active for cntr 1 interrupt timer a count stop bit 0 : count start 1 : count stop timer x timer x is an 8-bit timer and counts the prescaler x output. when timer x underflows, the timer x interrupt request bit is set to 1 . prescaler x is an 8-bit prescaler and counts the signal selected by the timer x count source selection bit. prescaler x and timer x have the prescaler x latch and the timer x latch to retain the reload value, respectively. the value of prescaler x latch is set to prescaler x when prescaler x underflows.the value of timer x latch is set to timer x when timer x underflows. when writing to prescaler x (prex) is executed, the value is writ- ten to both the prescaler x latch and prescaler x. when writing to timer x (tx) is executed, the value is written to both the timer x latch and timer x. when reading from prescaler x (prex) and timer x (tx) is ex- ecuted, each count value is read out. timer x can can be selected in one of 4 operating modes by set- ting the timer x operating mode bits of the timer x mode register. (1) timer mode prescaler x counts the count source selected by the timer x count source selection bits. each time the count clock is input, the con- tents of prescaler x is decremented by 1. when the contents of prescaler x reach 00 16 , an underflow occurs at the next count clock, and the prescaler x latch is reloaded into prescaler x and count continues. the division ratio of prescaler x is 1/(n+1) pro- vided that the value of prescaler x is n. the contents of timer x is decremented by 1 each time the under- flow signal of prescaler x is input. when the contents of timer x reach 00 16 , an underflow occurs at the next count clock, and the timer x latch is reloaded into timer x and count continues. the di- vision ratio of timer x is 1/(m+1) provided that the value of timer x is m. accordingly, the division ratio of prescaler x and timer x is 1/((n+1) ? (m+1)) provided that the value of prescaler x is n and the value of timer x is m. (2) pulse output mode in the pulse output mode, the waveform whose polarity is inverted each time timer x underflows is output from the cntr 0 pin. the output level of cntr 0 pin can be selected by the cntr 0 ac- tive edge switch bit. when the cntr 0 active edge switch bit is 0 , the output of cntr 0 pin is started at h level. when this bit is 1 , the output is started at l level. also, the inverted waveform of pulse output from cntr 0 pin can be output from tx out pin by setting 1 to the p0 3 /tx out output valid bit. when using a timer in this mode, set the port p1 4 and p0 3 direc- tion registers to output mode. (3) event counter mode the timer a counts signals input from the p1 4 /cntr 0 pin. except for this, the operation in event counter mode is the same as in timer mode. the active edge of cntr 0 pin input signal can be selected from rising or falling by the cntr 0 active edge switch bit . single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 25 (4) pulse width measurement mode in the pulse width measurement mode, the pulse width of the sig- nal input to p1 4 /cntr 0 pin is measured. the operation of timer x can be controlled by the level of the sig- nal input from the cntr 0 pin. when the cntr 0 active edge switch bit is 0 , the signal selected by the timer x count source selection bit is counted while the input signal level of cntr 0 pin is h . the count is stopped while the pin is l . also, when the cntr 0 active edge switch bit is 1 , the signal selected by the timer x count source selection bit is counted while the input signal level of cntr 0 pin is l . the count is stopped while the pin is h . timer x can stop counting by setting 1 to the timer x count stop bit in any mode. also, when timer x underflows, the timer x interrupt request bit is set to 1 . note on timer x is described below; note on timer x cntr 0 interrupt active edge selection cntr 0 interrupt active edge depends on the cntr 0 active edge switch bit. when this bit is 0 , the cntr 0 interrupt request bit is set to 1 at the falling edge of cntr 0 pin input signal. when this bit is 1 , the cntr 0 interrupt request bit is set to 1 at the rising edge of cntr 0 pin input signal. fig. 23 structure of timer x mode register fig. 24 timer count source set register timer x mode register (txm : address 002b 16 , initial value: 00 16 ) cntr 0 active edge switch bit 0 : interrupt at falling edge count at rising edge (in event counter mode) 1 : interrupt at rising edge count at falling edge (in event counter mode) timer x operating mode bits b1 b0 0 0 : timer mode 0 1 : pulse output mode 1 0 : event counter mode 1 1 : pulse width measurement mode not used (return 0 when read) timer x count stop bit 0 : count start 1 : count stop b7 b0 p0 3 /tx out output valid bit 0 : output invalid (i/o port) 1 : output valid (inverted cntr 0 output) timer count source set register (tcss : address 002e 16 , initial value: 00 16 ) b7 b0 timer x count source selection bits b1 b0 0 0 : f(x in )/16 0 1 : f(x in )/2 1 0 : f(x in ) (note 1) 1 1 : not available timer y count source selection bits b3 b2 0 0 : f(x in )/16 0 1 : f(x in )/2 1 0 : ring oscillator output (note 2) 1 1 : not available timer z count source selection bits b5 b4 0 0 : f(x in )/16 0 1 : f(x in )/2 1 0 : timer y underflow 1 1 : not available fix this bit to 0 . not used (return 0 when read) notes 1: f(x in ) can be used as timer x count source when using a ceramic resonator or ring oscillator. do not use it at rc oscillation. 2: system operates using a ring oscillator as a count source by setting the ring oscillator to oscillation enabled by bit 3 of cpum. single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 26 timer y timer y is an 8-bit timer and counts the prescaler y output. when timer y underflows, the timer y interrupt request bit is set to 1 . prescaler y is an 8-bit prescaler and counts the signal selected by the timer y count source selection bit. prescaler y has the prescaler y latch to retain the reload value. timer y has the timer y primary latch and timer y secondary latch to retain the reload value. the value of prescaler y latch is set to prescaler y when prescaler y underflows.the value of timer y primary latch or timer y secondary latch are set to timer y when timer y underflows. as for the value to transfer to timer y, either of timer y primary or timer y secondary is selected depending on the timer y operating mode. when writing to prescaler y (prey), timer y primary (typ) or timer y secondary (tys) is executed, writing to latch only or latch and prescaler (timer) can be selected by the setting value of the timer y write control bit. be sure to set the timer y write con- trol bit because there are some notes according to the operating mode. when reading from prescaler y (prey) is executed, the count value of prescaler y is read out. when reading from timer y pri- mary (typ) is executed, the count value of timer y is read out. the count value of timer y can be read out by reading from the timer y primary (typ) even when the value of timer y primary latch or timer y secondary latch is counted. when reading the timer y secondary (tys) is executed, the undefined value is read out. timer y can be selected in one of 2 operating modes by setting the timer y operating mode bits of the timer y, z mode register. (1) timer mode prescaler y counts the count source selected by the timer y count source selection bits. each time the count clock is input, the con- tents of prescaler y is decremented by 1. when the contents of prescaler y reach 00 16 , an underflow occurs at the next count clock, and the prescaler y latch is reloaded into prescaler y. the division ratio of prescaler y is 1/(n+1) provided that the value of prescaler y is n. the contents of timer y is decremented by 1 each time the under- flow signal of prescaler y is input. when the contents of timer y reach 00 16 , an underflow occurs at the next count clock, and the timer y primary latch is reloaded into timer y and count continues. (in the timer mode, the contents of timer y primary latch is counted. timer y secondary latch is not used in this mode.) the division ratio of timer y is 1/(m+1) provided that the value of timer y is m. accordingly, the division ratio of prescaler y and timer y is 1/((n+1) ? (m+1)) provided that the value of prescaler y is n and the value of timer y is m. in the timer mode, writing to latch only or latches and prescaler y and timer y primary can be selected by the setting value of the timer y write control bit. (2) programmable waveform generation mode in the programmable waveform generation mode, timer counts the setting value of timer y primary and the setting value of timer y secondary alternately, the waveform inverted each time timer y underflows is output from ty out pin. when using this mode, be sure to set 1 to the timer y write con- trol bit to select write to latch only . also, set the port p0 1 direction registers to output mode. the active edge of output waveform is set by the timer y output level latch (b5) of the timer y, z waveform output control register (pum). when 0 is set to b5 of pum, h interval by the setting value of typ or l interval by the setting value of tys is output alternately. when 1 is set to b5 of pum, l interval by the setting value of typ or h interval by the setting value of tys is output alternately. also, in this mode, the primary interval and the secondary interval of the output waveform can be extended respectively for 0.5 cycle of timer count source clock by setting the timer y primary wave- form extension control bit (b2) and the timer y secondary waveform extension control bit (b3) of pum to 1 . as a result, the waveforms of more accurate resolution can be output. when b2 and b3 of pum are used, the frequency and duty of the output waveform are as follows; waveform frequency: fyout= duty: dyout= tmycl: timer y count source (frequency) typ: timer y primary (8bit) tys: timer y secondary (8bit) expyp: timer y primary waveform extension control bit (1bit) expys: timer y secondary waveform extension control bit (1bit) in the programmable waveform generation mode, when values of the typ, tys, expyp and expys are changed, the output wave- form is changed at the beginning (timer y primary waveform interval) of waveform period. when the count values are changed, set values to the tys, expyp and expys first. after then, set the value to typ. the val- ues are set all at once at the beginning of the next waveform period when the value is set to typ. (when writing at timer stop is executed, writing to typ at last is required.) notes on programmable waveform generation mode is described below; 2 ? tmycl 2 ? (typ+1)+2 ? (tys+1)+(expyp+expys) 2 ? (typ+1)+expyp (2 ? (typ+1)+expyp)+(2 ? (tys+1)+expys) single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 27 notes on programmable generation waveform mode count set value in the programmable waveform generation mode, values of tys, expyp, and expys are valid by writing to typ because the set- ting to them is executed all at once by writing to typ. even when changing typ is not required, write the same value again. write timing to typ in the programmable waveform generation mode, when the set- ting value is changed while the waveform is output, set by software in order not to execute the writing to typ and the timing of timer underflow during the secondary interval simultanesously. usage of waveform extension function the waveform extension function by the timer y waveform exten- sion control bit can be used only when 00 16 is set to prescaler y. when the value other than 00 16 is set to prescaler y, be sure to set 0 to expyp and expys. timer y write mode when using this mode, be sure to set 1 to the timer y write con- trol bit to select write to latch only . timer y can stop counting by setting 1 to the timer y count stop bit in any mode. also, when timer y underflows, the timer y interrupt request bit is set to 1 . timer y reloads the value of latch when counting is stopped by the timer y count stop bit. (when timer is read out while timer is stopped, the value of latch is read. the value of timer can be read out only while timer is operating.) single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 28 timer z timer z is an 8-bit timer and counts the prescaler z output. when timer z underflows, the timer z interrupt request bit is set to 1 . prescaler z is an 8-bit prescaler and counts the signal selected by the timer z count source selection bit. prescaler z has the prescaler z latch to retain the reload value. timer z has the timer z primary latch and timer z secondary latch to retain the reload value. the value of prescaler z latch is set to prescaler z when prescaler z underflows.the value of timer z primary latch or timer z second- ary latch are set to timer z when timer z underflows. as for the value to transfer to timer z, either of timer z primary or timer z secondary is selected depending on the timer z operating mode. when writing to prescaler z (prez), timer z primary (tzp) or timer z secondary (tzs) is executed, writing to latch only or latches and prescaler z and timer z can be selected by the set- ting value of the timer z write control bit. be sure to set the write control bit because there are some notes according to the operat- ing mode. when reading from prescaler z (prez) is executed, the count value of prescaler z is read out. when reading from timer z pri- mary (tzp) is executed, the count value of timer z is read out. the count value of timer z can be read out by reading from the timer z primary (tzp) even when the value of timer z primary latch or timer z secondary latch is counted. when reading the timer z secondary (tzs) is executed, the undefined value is read out. timer z can be selected in one of 4 operating modes by setting the timer z operating mode bits of the timer y, z mode register. (1) timer mode prescaler z counts the count source selected by the timer z count source selection bits. each time the count clock is input, the con- tents of prescaler z is decremented by 1. when the contents of prescaler z reach 00 16 , an underflow occurs at the next count clock, and the prescaler z latch is reloaded into prescaler z. the division ratio of prescaler z is 1/(n+1) provided that the value of prescaler z is n. the contents of timer z is decremented by 1 each time the under- flow signal of prescaler z is input. when the contents of timer z reach 00 16 , an underflow occurs at the next count clock, and the timer z primary latch is reloaded into timer z and count continues. (in the timer mode, the contents of timer z primary latch is counted. timer z secondary latch is not used in this mode.) the division ratio of timer z is 1/(m+1) provided that the value of timer z is m. accordingly, the division ratio of prescaler z and timer z is 1/((n+1) ? (m+1)) provided that the value of prescaler z is n and the value of timer z is m. in the timer mode, writing to latch only or latches and prescaler z and timer z primary can be selected by the setting value of the timer z write control bit. (2) programmable waveform generation mode in the programmable waveform generation mode, timer counts the setting value of timer z primary and the setting value of timer z secondary alternately, the waveform inverted each time timer z underflows is output from tz out pin. when using this mode, be sure to set 1 to the timer z write con- trol bit to select write to latch only . also, set the port p0 2 direction registers to output mode. the active edge of output waveform is set by the timer z output level latch (b4) of the timer y, z waveform output control register (pum). when 0 is set to b4 of pum, h interval by the setting value of tzp or l interval by the setting value of tzs is output al- ternately. when 1 is set to b4 of pum, l interval by the setting value of tzp or h interval by the setting value of tzs is output alternately. also, in this mode, the primary interval and the secondary interval of the output waveform can be extended respectively for 0.5 cycle of timer count source clock by setting the timer z primary wave- form extension control bit (b0) and the timer z secondary waveform extension control bit (b1) of pum to 1 . as a result, the waveforms of more accurate resolution can be output. when b0 and b1 of pum are used, the frequency and duty of the output waveform are as follows; waveform frequency: fzout= duty: dzout= tmzcl: timer z count source (frequency) tzp: timer z primary (8bit) tzs: timer z secondary (8bit) expzp: timer z primary waveform extension control bit (1bit) expzs: timer z secondary waveform extension control bit (1bit) in the programmable waveform generation mode, when values of the tzp, tzs, expzp and expzs are changed, the output wave- form is changed at the beginning (timer z primary waveform interval) of waveform period. when the count values are changed, set values to the tzs, expzp and expzs first. after then, set the value to tzp. the val- ues are set all at once at the beginning of the next waveform period when the value is set to tzp. (when writing at timer stop is executed, writing to tzp at last is required.) 2 ? tmzcl 2 ? (tzp+1)+2 ? (tzs+1)+(expzp+expzs) 2 ? (tzp+1)+expzp (2 ? (tzp+1)+expzp)+(2 ? (tzs+1)+expzs single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 29 notes on the programmable waveform generation mode are de- scribed below; notes on programmable waveform generation mode count set value in the programmable waveform generation mode, values of tzs, expzp, and expzs are valid by writing to tzp because the set- ting to them is executed all at once by writing to tzp. even when changing tzp is not required, write the same value again. write timing to tzp in the programmable waveform generation mode, when the set- ting value is changed while the waveform is output, set by software in order not to execute the writing to tzp and the timing of timer underflow during the secondary interval simultanesously. usage of waveform extension function the waveform extension function by the timer z waveform exten- sion control bit can be used only when 00 16 is set to prescaler z. when the value other than 00 16 is set to prescaler z, be sure to set 0 to expzp and expzs. also, when the timer y underflow is selected as the count source, the waveform extension function cannot be used. timer z write mode when using this mode, be sure to set 1 to the timer z write con- trol bit to select write to latch only . (3) programmable one-shot generation mode in the programmable one-shot generation mode, the one-shot pulse by the setting value of timer z primary can be output from tz out pin by software or external trigger. when using this mode, be sure to set 1 to the timer z write control bit to select write to latch only . also, set the port p0 2 direction registers to output mode. in this mode, tzs is not used. the active edge of output waveform is set by the timer z output level latch (b5) of the timer y, z waveform output control register (pum). when 0 is set to b5 of pum, h pulse during the interval of the tzp setting value is output. when 1 is set to b5 of pum, l pulse during the interval of the tzp setting value is output. also, in this mode, the interval of the one-shot pulse output can be extended for 0.5 cycle of timer count source clock by setting the timer z primary waveform extension control bit (b2) of pum to 1 . as a result, the waveforms of more accurate resolution can be output. in the programmable one-shot generation mode, the trigger by software or the external int 0 pin can be accepted by writing 0 to the timer z count stop bit after the count value is set. (at the time when 0 is written to the timer z count stop bit, timer z stops.) by writing 1 to the timer z one-shot start bit, or by inputting the valid trigger to the int 0 pin after the trigger to the int 0 pin be- comes valid by writing 1 to the int 0 pin one-shot trigger control bit, timer z starts counting, at the same time, the output of tz out pin is inverted. when timer z underflows, the output of tz out pin is inverted again and timer z stops. when also the trigger of int 0 pin is accepted, the contents of the one-shot start bit is changed to 1 by hardware. the falling or rising can be selected as the edge of the valid trig- ger of int 0 pin by the int 0 pin one-shot trigger edge selection bit. during the one-shot pulse output interval, the one-shot pulse out- put can be stopped forcibly by writing 0 to the timer z one-shot start bit. in the programmable one-shot generation mode, when the count values are changed, set value to the expzp first. after then, set the value to tzp. the values are set all at once at the beginning of the next one-shot pulse when the value is set to tzp. (when writ- ing at timer stop is executed, writing to tzp at last is required.) notes on the programmable one-shot generation mode are de- scribed below; notes on programmable one-shot generation mode count set value in the programmable one-shot generation mode, the value of expzp becomes valid by writing to tzp. even when changing tzp is not required, write the same value again. write timing to tzp in the programmable one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to tzp and the timing of timer un- derflow simultanesously. usage of waveform extension function the waveform extension function by the timer z waveform exten- sion control bit can be used only when 00 16 is set to prescaler z. when the value other than 00 16 is set to prescaler z, be sure to set 0 to expzp. also, when the timer y underflow is selected as the count source, the waveform extension function cannot be used. timer z write mode when using this mode, be sure to set 1 to the timer z write con- trol bit to select write to latch only . single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 30 (4) programmable wait one-shot generation mode in the programmable wait one-shot generation mode, the one-shot pulse by the setting value of timer z secondary can be output from tz out pin by software or external trigger to int 0 pin after the wait by the setting value of the timer z primary. when using this mode, be sure to set 1 to the timer z write control bit to select write to latch only . also, set the port p0 2 direction registers to output mode. the active edge of output waveform is set by the timer z output level latch (b5) of the timer y, z waveform output control register (pum). when 0 is set to b5 of pum, after the wait during the in- terval of the tzp setting value, h pulse during the interval of the tzs setting value is output. when 1 is set to b5 of pum, after the wait during the interval of the tzp setting value, l pulse during the interval of the tzs setting value is output. also, in this mode, the intervals of the wait and the one-shot pulse output can be extended for 0.5 cycle of timer count source clock by setting expzp and expzs of pum to 1 . as a result, the waveforms of more accurate resolution can be output. in the programmable one-shot generation mode, the trigger by software or the external int 0 pin can be accepted by writing 0 to the timer z count stop bit after the count value is set. (at the time when 0 is written to the timer z count stop bit, timer z stops.) by writing 1 to the timer z one-shot start bit, or by inputting the valid trigger to the int 0 pin after the trigger to the int 0 pin be- comes valid by writing 1 to the int 0 pin one-shot trigger control bit, timer z starts counting. while timer z counts the tzp, the initial value of the tz out pin output is retained. when timer z underflows, the value of tzs is reloaded, at the same time, the output of tz out pin is inverted. when timer z underflows, the output of tz out pin is inverted again and timer z stops. when also the trigger of int 0 pin is ac- cepted, the contents of the one-shot start bit is changed to 1 by hardware. the falling or rising can be selected as the edge of the valid trig- ger of int 0 pin by the int 0 pin one-shot trigger edge selection bit. during the wait interval and the one-shot pulse output interval, the one-shot pulse output can be stopped forcibly by writing 0 to the timer z one-shot start bit. in the programmable wait one-shot generation mode, when the count values are changed, set values to the tzs, expzp and expzs first. after then, set the value to tzp. the values are set all at once at the beginning of the next wait interval when the value is set to tzp. (when writing at timer stop is executed, writing to tzp at last is required.) notes on the programmable wait one-shot generation mode are described below; notes on programmable wait one-shot generation mode count set value in the programmable wait one-shot generation mode, values of tzs, expzp and expzs are valid by writing to tzp. even when changing tzp is not required, write the same value again. write timing to tzp in the programmable wait one-shot generation mode, when the setting value is changed while the waveform is output, set by soft- ware in order not to execute the writing to tzp and the timing of timer underflow during the secondary interval simultanesously. usage of waveform extension function the waveform extension function by the timer z waveform exten- sion control bit can be used only when 00 16 is set to prescaler z. when the value other than 00 16 is set to prescaler z, be sure to set 0 to expzp and expzs. also, when the timer y underflow is selected as the count source, the waveform extension function cannot be used. timer z write mode when using this mode, be sure to set 1 to the timer z write con- trol bit to select write to latch only . timer z can stop counting by setting 1 to the timer z count stop bit in any mode. also, when timer z underflows, the timer z interrupt request bit is set to 1 . timer z reloads the value of latch when counting is stopped by the timer z count stop bit. (when timer is read out while timer is stopped, the value of latch is read. the value of timer can be read out only while timer is operating.) single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 31 fig. 26 structure of timer yz waveform output control register fig. 27 structure of one-shot start register fig. 25 structure of timer y, z mode register b7 b0 timer y, z mode register (tyzm : address 0020 16 , initial value: 00 16 ) timer y operating mode bit 0 : timer mode 1 : programmable waveform generation mode not used (return 0 when read) timer y write control bit 0 : write to latch and timer simultaneously 1 : write to only latch timer y count stop bit 0 : count start 1 : count stop timer z operating mode bits b5 b4 0 0 : timer mode 0 1 : programmable waveform generation mode 1 0 : programmable one-shot generation mode 1 1 : programmable wait one-shot generation mode timer z write control bit 0 : write to latch and timer simultaneously 1 : write to only latch timer z count stop bit 0 : count start 1 : count stop b7 b0 timer y, z waveform output control register (pum : address 0024 16 , initial value: 00 16 ) timer y primary waveform extension control bit 0 : waveform not extended 1 : waveform extended timer y secondary waveform extension control bit 0 : waveform not extended 1 : waveform extended timer z primary waveform extension control bit 0 : waveform not extended 1 : waveform extended timer z secondary waveform extension control bit 0 : waveform not extended 1 : waveform extended timer y output level latch 0 : l output 1 : h output timer z output level latch 0 : l output 1 : h output int 0 pin one-shot trigger control bit 0 : int 0 pin one-shot trigger invalid 1 : int 0 pin one-shot trigger valid int 0 pin one-shot trigger active edge selection bit 0 : falling edge trigger 1 : rising edge trigger b7 b0 one-shot start register (ons : address 002a 16 , initial value: 00 16 ) timer z one-shot start bit 0 : one-shot stop 1 : one-shot start not used (return 0 when read) single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 32 fig. 28 block diagram of timer 1 and timer a timer a (low-order) latch (8) timer a (low-order) (8) timer a (high-order) latch (8) timer a (high-order) (8) data bus p0 0 /cntr 1 cntr 1 active edge switch bit f(x in )/16 rising edge detected falling edge detected timer a operation mode bit timer a count stop bit prescaler 1 latch (8) prescaler 1 (8) timer 1 latch (8) timer 1 (8) f(x in )/16 data bus timer a interrupt request bit timer 1 interrupt request bit pulse width hl continuously measurement mode period measurement mode single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 33 fig. 29 block diagram of timer x, timer y and timer z q q t toggle flip-flop timer y count stop bit programmable waveform gengeration mode f(x in )/16 f(x in )/2 timer y count source selection bits waveform extension function timer y primary waveform extension control bit p0 1 /ty out timer y output level latch q q t f(x in )/16 waveform extension function timer z primary waveform extenstion control bit p0 2 /tz out int 0 interrupt request bit p3 7 /int 0 f(x in )/2 timer z count stop bit ring oscillator clock ring (ring oscillator output in fig. 50, 51) q q p1 4 /cntr 0 r t f(x in )/16 f(x in )/2 timer x interrupt request bit toggle flip-flop timer x count stop bit pulse width measurement mode event counter mode cntr 0 interrupt request bit pulse output mode port p1 4 latch port p1 4 direction register cntr 0 active edge switch bit timer mode pulse output mode cntr 0 active edge switch bit timer x count source selection bits f(x in ) p0 3 /tx out prescaler x latch (8) prescaler x (8) timer x latch (8) timer x (8) data bus 0 1 0 1 writing to timer x latch pulse output mode p0 3 /tx out output valid port p0 3 latch port p0 3 direction register prescaler y latch (8) prescaler y (8) timer y primary latch (8) timer y (8) data bus timer y secondary latch (8) timer y interrupt request bit port p0 1 latch port p0 1 direction register timer y secondary waveform extension control bit prescaler z latch (8) prescaler z (8) timer z primary latch (8) timer z (8) data bus timer z secondary latch (8) timer z interrupt request bit timer z count source selection bits one-shot pulse trigger input int 0 pin trigger active edge selection bit programmable one-shot generation mode programmable wait one-shot generation mode timer z one-shot start bit timer z secondary waveform extenstion control bit port p0 2 latch port p0 2 direction register toggle flip flop timer z output level latch programmable waveform generation mode programmable one-shot generation mode single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 34 fig. 30 block diagram of clock synchronous serial i/o1 fig. 31 operation of clock synchronous serial i/o1 function serial i/o serial i/o1 serial i/o1 can be used as either clock synchronous or asynchro- nous (uart) serial i/o. a dedicated timer is also provided for baud rate generation. (1) clock synchronous serial i/o mode clock synchronous serial i/o1 mode can be selected by setting the serial i/o1 mode selection bit of the serial i/o1 control register (bit 6) to 1 . for clock synchronous serial i/o1, the transmitter and the receiver must use the same clock. if an internal clock is used, transfer is started by a write signal to the tb/rb. 1/4 1/4 f/f p1 2 /s clk1 serial i/o1 status register serial i/o1 control register p1 3 /s rdy1 p1 0 /r x d 1 p1 1 /t x d 1 x in receive buffer register address 0018 16 receive shift register receive buffer full flag (rbf) receive interrupt request (ri) clock control circuit shift clock serial i/o1 synchronous clock selection bit frequency division ratio 1/(n+1) baud rate generator address 001c 16 brg count source selection bit clock control circuit falling-edge detector transmit buffer register data bus address 0018 16 shift clock transmit shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) transmit interrupt source selection bit address 0019 16 data bus address 001a 16 transmit shift register d 7 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 rbf = 1 tsc = 1 tbe = 0 tbe = 1 tsc = 0 transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) serial output txd serial input rxd write pulse to receive/transmit buffer register (address 0018 16 ) overrun error (oe) detection notes 1: as the transmit interrupt (ti), which can be selected, either when the transmit buffer has emptied (tbe=1) or after the transmit shift operation has ended (tsc=1), by setting the transmit interrupt source selection bit (tic) of the serial i/o1 control register. 2: if data is written to the transmit buffer register when tsc=0, the transmit clock is generated continuously and serial data is output continuously from the txd pin. 3: the receive interrupt (ri) is set when the receive buffer full flag (rbf) becomes 1 . receive enable signal s rdy1 single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 35 fig. 32 block diagram of uart serial i/o1 (2) asynchronous serial i/o (uart) mode clock asynchronous serial i/o mode (uart) can be selected by clearing the serial i/o1 mode selection bit of the serial i/o1 control register to 0 . eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. x in 1/4 oe pe fe 1/16 1/16 data bus receive buffer register address 0018 16 receive shift register receive buffer full flag (rbf) receive interrupt request (ri) baud rate generator frequency division ratio 1/(n+1) address 001c 16 st/sp/pa generator transmit buffer register data bus transmit shift register address 0018 16 transmit shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) address 0019 16 st detector sp detector uart control register address 001b 16 character length selection bit address 001a 16 brg count source selection bit transmit interrupt source selection bit serial i/o1 synchronous clock selection bit clock control circuit character length selection bit 7 bits 8 bits serial i/o1 control register p1 2 /s clk1 serial i/o1 status register p1 0 /r x d 1 p1 1 /t x d 1 the transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. since the shift reg- ister cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. the transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. fig. 33 operation of uart serial i/o1 function tsc=0 tbe=1 rbf=0 tbe=0 tbe=0 rbf=1 rbf=1 st d 0 d 1 sp d 0 d 1 st sp tbe=1 tsc=1 st d 0 d 1 sp d 0 d 1 st sp transmit or receive clock transmit buffer write signal generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) 1: error flag detection occurs at the same time that the rbf flag becomes 1 (at 1st stop bit, during reception). 2: as the transmit interrupt (ti), when either the tbe or tsc flag becomes 1, can be selected to occur depending on the setting of the transmit interrupt source selection bit (tic) of the serial i/o1 control register. 3: the receive interrupt (ri) is set when the rbf flag becomes 1. 4: after data is written to the transmit buffer when tsc=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to tsc=0. notes ? ? serial output t x d serial input r x d receive buffer read signal single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 36 [transmit buffer register/receive buffer register (tb/rb)] 0018 16 the transmit buffer register and the receive buffer register are lo- cated at the same address. the transmit buffer is write-only and the receive buffer is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer is 0 . [serial i/o1 status register (sio1sts)] 0019 16 the read-only serial i/o1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o1 function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to 0 when the receive buffer register is read. if there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. a write to the serial i/o1 status register clears all the error flags oe, pe, fe, and se (bit 3 to bit 6, respectively). writing 0 to the serial i/o1 enable bit sioe (bit 7 of the serial i/o1 control register) also clears all the status flags, including the error flags. bits 0 to 6 of the serial i/o1 status register are initialized to 0 at reset, but if the transmit enable bit of the serial i/o1 control regis- ter has been set to 1 , the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become 1 . [serial i/o1 control register (sio1con)] 001a 16 the serial i/o1 control register consists of eight control bits for the serial i/o1 function. [uart control register (uartcon)] 001b 16 the uart control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial i/o is selected and set the data format of an data transfer and one bit (bit 4) which is al- ways valid and sets the output structure of the p1 1 /txd 1 pin. [baud rate generator (brg)] 001c 16 the baud rate generator determines the baud rate for serial transfer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. notes on serial i/o serial i/o interrupt when setting the transmit enable bit to 1 , the serial i/o transmit interrupt request bit is automatically set to 1 . when not requiring the interrupt occurrence synchronized with the transmission en- abled, take the following sequence. ? set the serial i/o transmit interrupt enable bit to 0 (disabled). ? set the transmit enable bit to 1 . ? set the serial i/o transmit interrupt request bit to 0 after 1 or more instructions have been executed. ? set the serial i/o transmit interrupt enable bit to 1 (enabled). i/o pin function when serial i/o1 is enabled. the functions of p1 2 and p1 3 are switched with the setting values of a serial i/o1 mode selection bit and a serial i/o1 synchronous clock selection bit as follows. (1) serial i/o1 mode selection bit 1 : clock synchronous type serial i/o is selected. setup of a serial i/o1 synchronous clock selection bit 0 : p1 2 pin turns into an output pin of a synchronous clock. 1 : p1 2 pin turns into an input pin of a synchronous clock. setup of a srdy1 output enable bit (srdy) 0 : p1 3 pin can be used as a normal i/o pin. 1 : p1 3 pin turns into a srdy output pin. (2) serial i/o1 mode selection bit 0 : clock asynchronous (uart) type serial i/o is selected. setup of a serial i/o1 synchronous clock selection bit 0 : p1 2 pin can be used as a normal i/o pin. 1 : p1 2 pin turns into an input pin of an external clock. when clock asynchronous (uart) type serial i/o is selected, it is p1 3 pin. it can be used as a normal i/o pin. single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 37 fig. 34 structure of serial i/o1-related registers b7 b7 transmit buffer empty flag (tbe) 0: buffer full 1: buffer empty receive buffer full flag (rbf) 0: buffer empty 1: buffer full transmit shift completion flag (tsc) 0: transmit shift in progress 1: transmit shift completed overrun error flag (oe) 0: no error 1: overrun error parity error flag (pe) 0: no error 1: parity error framing error flag (fe) 0: no error 1: framing error summing error flag (se) 0: (oe) u (pe) u (fe)=0 1: (oe) u (pe) u (fe)=1 not used (returns 1 when read) serial i/o1 status register serial i/o1 control register b0 b0 brg count source selection bit (css) 0: f(x in ) 1: f(x in )/4 serial i/o1 synchronous clock selection bit (scs) 0: brg output divided by 4 when clock synchronous serial i/o is selected, brg output divided by 16 when uart is selected. 1: external clock input when clock synchronous serial i/o is selected, external clock input divided by 16 when uart is selected. s rdy1 output enable bit (srdy) 0: p1 3 pin operates as ordinary i/o pin 1: p1 3 pin operates as s rdy1 output pin transmit interrupt source selection bit (tic) 0: interrupt when transmit buffer has emptied 1: interrupt when transmit shift operation is completed transmit enable bit (te) 0: transmit disabled 1: transmit enabled receive enable bit (re) 0: receive disabled 1: receive enabled serial i/o1 mode selection bit (siom) 0: clock asynchronous (uart) serial i/o 1: clock synchronous serial i/o serial i/o1 enable bit (sioe) 0: serial i/o1 disabled (pins p1 0 to p1 3 operate as ordinary i/o pins) 1: serial i/o1 enabled (pins p1 0 to p1 3 operate as serial i/o pins) b7 uart control register character length selection bit (chas) 0: 8 bits 1: 7 bits parity enable bit (pare) 0: parity checking disabled 1: parity checking enabled parity selection bit (pars) 0: even parity 1: odd parity stop bit length selection bit (stps) 0: 1 stop bit 1: 2 stop bits p1 1 /t x d 1 p-channel output disable bit (poff) 0: cmos output (in output mode) 1: n-channel open drain output (in output mode) not used (return 1 when read) b0 (sio1sts : address 0019 16 , initial value: 00 16 ) (sio1con : address 001a 16 , initial value: 00 16 ) (uartcon : address 001b 16 , initial value: e0 16 ) single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 38 serial i/o2 the serial i/o2 function can be used only for clock synchronous serial i/o. for clock synchronous serial i/o2 the transmitter and the receiver must use the same clock. when the internal clock is used, transfer is started by a write signal to the serial i/o2 register. note: serial i/o2 can be used in the following cases; (1) serial i/o1 is not used, (2) serial i/o1 is used as uart and brg output divided by 16 is selected as the synchronized clock. [serial i/o2 control register] sio2con the serial i/o2 control register contains 8 bits which control vari- ous serial i/o functions. set 0 to bit 3 to receive. at reception, clear bit 7 to 0 by writing a dummy data to the se- rial i/o2 register after completion of shift. fig. 35 structure of serial i/o2 control registers fig. 36 block diagram of serial i/o2 internal synchronous clock selection bits 000 : f(x in )/8 001 : f(x in )/16 010 : f(x in )/32 011 : f(x in )/64 110 : f(x in )/128 111 : f(x in )/256 b7 b0 not used (returns 0 when read) transfer direction selection bit 0 : lsb first 1 : msb first s clk2 pin selection bit 0 : external clock (s clk2 is an input) 1 : internal clock (s clk2 is an output) transmit / receive shift completion flag 0 : shift in progress 1 : shift completed note : when using it as a s data input, set the port p1 3 direction register to 0 . serial i/o2 control register (sio2con: address 0030 16 , initila value: 00 16 ) s data2 pin selection bit (note) 0 : i/o port / s data2 input 1 : s data2 output 1 0 0 1 0 1 1/8 1/16 1/32 1/64 1/128 1/256 x in data bus serial i/o2 interrupt request s data2 pin selection bit serial i/o counter 2 (3) serial i/o shift register 2 (8) s clk2 pin selection bit internal synchronous clock selection bits divider p1 2 /s clk2 p1 3 /s data2 p1 2 latch s clk2 pin selection bit s clk p1 3 latch s data2 pin selection bit single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 39 serial i/o2 operation by writing to the serial i/o2 register (address 0031 16 ) the serial i/ o2 counter is set to 7 . after writing, the s data2 pin outputs data every time the transfer clock shifts from h to l . and, as the transfer clock shifts from l to h , the s data2 pin reads data, and at the same time the contents of the serial i/o2 register are shifted by 1 bit. when the internal clock is selected as the transfer clock source, the following operations execute as the transfer clock counts up to 8. serial i/o2 counter is cleared to 0 . transfer clock stops at an h level. interrupt request bit is set. shift completion flag is set. also, the s data2 pin is in a high impedance state after the data transfer is completed (refer to fig.37). when the external clock is selected as the transfer clock source, the interrupt request bit is set as the transfer clock counts up to 8, but external control of the clock is required since it does not stop. notice that the s data2 pin is not in a high impedance state on the completion of data transfer. also, after the receive operation is completed, the transmit/receive shift completion flag is cleared by reading the serial i/o2 register. at transmit, the transmit/receive shift completion flag is cleared and the transmit operation is started by writing to serial i/o2 regis- ter. fig. 37 serial i/o2 timing (lsb first) d 0 note : synchronous clock serial i/o2 register write signal transfer clock (note) s data2 at serial i/o2 input receive s data2 at serial i/o2 output transmit serial i/o2 interrupt request bit set transmit/receive shift completion flag set d 1 d 2 d 3 d 4 d 5 d 6 d 7 when the internal clock is selected as the transfer and the direction register of p1 3 /s data2 pin is set to the input mode, the s data2 pin is in a high impedance state after the data transfer is completed. single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 40 a-d converter the functional blocks of the a-d converter are described below. [a-d conversion register] ad the a-d conversion register is a read-only register that stores the result of a-d conversion. do not read out this register during an a- d conversion. [a-d control register] adcon the a-d control register controls the a-d converter. bit 2 to 0 are analog input pin selection bits. bit 4 is the ad conversion comple- tion bit. the value of this bit remains at 0 during a-d conversion, and changes to 1 at completion of a-d conversion. a-d conversion is started by setting this bit to 0 . [comparison voltage generator] the comparison voltage generator divides the voltage between av ss and v ref by 1024, and outputs the divided voltages. [channel selector] the channel selector selects one of ports p2 7 /an 7 to p2 0 /an 0 , and inputs the voltage to the comparator. [comparator and control circuit] the comparator and control circuit compares an analog input volt- age with the comparison voltage and stores its result into the a-d conversion register. when a-d conversion is completed, the con- trol circuit sets the ad conversion completion bit and the ad interrupt request bit to 1 . because the comparator is constructed linked to a capacitor, set f(x in ) to 500 khz or more during a-d con- version. fig. 38 structure of a-d control register fig. 39 structure of a-d conversion register fig. 40 block diagram of a-d converter a-d control register (adcon : address 0034 16 , initial value: 10 16 ) not used (returns 0 when read) not used (returns 0 when read) ad conversion completion bit 0 : conversion in progress 1 : conversion completed b7 b0 analog input pin selection bits 000 : p2 0 /an 0 001 : p2 1 /an 1 010 : p2 2 /an 2 011 : p2 3 /an 3 100 : p2 4 /an 4 101 : p2 5 /an 5 110 : p2 6 /an 6 (note) 111 : p2 7 /an 7 (note) note: these can be used only for 36 pin version. read 8-bit (read only address 0035 16 ) b7 b0 b9 b8 b7 b6 b5 b4 b3 b2 (address 0035 16 ) read 10-bit (read in order address 0036 16 , 0035 16 ) b7 b0 b9 b8 (address 0036 16 ) b7 b0 b7 b6 b5 b4 b3 b2 b1 b0 (address 0035 16 ) note: high-order 6-bit of address 0036 16 returns 0 when read. a-d control register (address 0034 16 ) channel selector a-d control circuit resistor ladder v ref comparator a-d interrupt request b7 b0 data bus 3 10 p2 0 /an 0 p2 1 /an 1 p2 2 /an 2 p2 3 /an 3 p2 4 /an 4 p2 5 /an 5 p2 6 /an 6 p2 7 /an 7 a-d conversion register (low-order) (address 0036 16 ) (address 0035 16 ) a-d conversion register (high-order) v ss single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 41 watchdog timer the watchdog timer gives a means for returning to a reset status when the program fails to run on its normal loop due to a runaway. the watchdog timer consists of an 8-bit watchdog timer h and an 8-bit watchdog timer l, being a 16-bit counter. standard operation of watchdog timer the watchdog timer stops when the watchdog timer control regis- ter (address 0039 16 ) is not set after reset. writing an optional value to the watchdog timer control register (address 0039 16 ) causes the watchdog timer to start to count down. when the watchdog timer h underflows, an internal reset occurs. accord- ingly, it is programmed that the watchdog timer control register (address 0039 16 ) can be set before an underflow occurs. when the watchdog timer control register (address 0039 16 ) is read, the values of the high-order 6-bit of the watchdog timer h, stp instruction disable bit and watchdog timer h count source se- lection bit are read. initial value of watchdog timer by a reset or writing to the watchdog timer control register (ad- dress 0039 16 ), the watchdog timer h is set to ff 16 and the watchdog timer l is set to ff 16 . operation of watchdog timer h count source selection bit a watchdog timer h count source can be selected by bit 7 of the watchdog timer control register (address 0039 16 ). when this bit is 0 , the count source becomes a watchdog timer l underflow sig- nal. the detection time is 131.072 ms at f(x in )=8 mhz. when this bit is 1 , the count source becomes f(x in )/16. in this case, the detection time is 512 s at f(x in )=8 mhz. this bit is cleared to 0 after reset. operation of stp instruction disable bit when the watchdog timer is in operation, the stp instruction can be disabled by bit 6 of the watchdog timer control register (ad- dress 0039 16 ). when this bit is 0 , the stp instruction is enabled. when this bit is 1 , the stp instruction is disabled, and an inter- nal reset occurs if the stp instruction is executed. once this bit is set to 1 , it cannot be changed to 0 by program. this bit is cleared to 0 after reset. fig. 41 block diagram of watchdog timer fig. 42 structure of watchdog timer control register x in data bus 0 1 1/16 watchdog timer h count source selection bit reset circuit stp instruction disable bit watchdog timer h (8) write "ff 16 " to the watchdog timer control register internal reset reset watchdog timer l (8) stp instruction write ff 16 to the watchdog timer control register watchdog timer control register (wdtcon: address 0039 16 , initial value: 3f 16 ) watchdog timer h (read only for high-order 6-bit) stp instruction disable bit 0 : stp instruction enabled 1 : stp instruction disabled watchdog timer h count source selection bit 0 : watchdog timer l underflow 1 : f(x in )/16 b7 b0 single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 42 reset circuit the microcomputer is put into a reset status by holding the re- set pin at the l level for 2 s or more when the power source voltage is 2.2 to 5.5 v and x in is in stable oscillation. after that, this reset status is released by returning the reset pin to the h level. the program starts from the address having the contents of address fffd 16 as high-order address and the con- tents of address fffc 16 as low-order address. in the case of f( ) 6 mhz, the reset input voltage must be 0.9 v or less when the power source voltage passes 4.5 v. in the case of f( ) 4 mhz, the reset input voltage must be 0.8 v or less when the power source voltage passes 4.0 v. in the case of f( ) 2 mhz, the reset input voltage must be 0.48 v or less when the power source voltage passes 2.4 v. in the case of f( ) 1 mhz, the reset input voltage must be 0.44 v or less when the power source voltage passes 2.2 v. fig. 43 example of reset circuit fig. 44 timing diagram at reset (note) 0.2 v cc 0 v 0 v poweron v cc reset v cc reset power source voltage detection circuit power source voltage reset input voltage note : reset release voltage vcc = 2.2 v data address 8-13 clock cycles reset address from the vector table 1 : a built-in ring oscillator applies about ring 2 mhz, 250 khz frequency clock at average of vcc = 5 v. 2 : the mark ? means that the address is changeable depending on the previous state. 3 : these are all internal signals except reset. notes ?? fffc fffd ad h ,ad l ??? ?? ad l ad h ??? clock from built-in ring oscillator ring reset reset out sync single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 43 fig. 45 internal status of microcomputer at reset prescaler 1 timer 1 one-shot start register timer x mode register prescaler x timer x timer count source set register serial i/o2 control register a-d control register misrg watchdog timer control register interrupt edge selection register cpu mode register interrupt request register 1 interrupt control register 1 processor status register program counter (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) contents of address fffc 16 (pc h ) (pc l ) ff 16 01 16 00 16 00 16 ff 16 ff 16 00 16 00 16 10 16 00 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 0030 16 0034 16 0038 16 0039 16 003a 16 003b 16 003c 16 003e 16 (ps) note x : undefined contents of address fffd 16 0011 1111 00 16 00 16 00 16 1000 0000 xxxx x1xx port p0 direction register port p1 direction register port p2 direction register port p3 direction register pull-up control register (1) (2) (3) (4) (5) register contents 00 16 00 16 00 16 00 16 0001 16 0003 16 0005 16 0007 16 0016 16 serial i/o1 control register uart control register (8) (9) serial i/o1 status register (7) 001a 16 001b 16 00 16 1110 0000 0019 16 1000 0000 xx x 0 0000 address port p1p3 control register (6) 0017 16 00 16 timer a mode register timer a (low-order) timer a (high-order) 00 16 ff 16 ff 16 001d 16 001e 16 001f 16 timer y, z mode register prescaler y timer y secondary 00 16 ff 16 ff 16 0020 16 0021 16 0022 16 timer y primary timer y, z waveform output control register prescaler z ff 16 00 16 ff 16 0023 16 0024 16 0025 16 timer z secondary ff 16 0026 16 timer z primary ff 16 0027 16 (27) (28) (29) (30) (31) (32) (33) (34) (35) (36) serial i/o2 register 00 16 0031 16 interrupt request register 2 003d 16 00 16 interrupt control register 2 003f 16 00 16 (37) (38) (39) (40) single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 44 fig. 46 external circuit of ceramic resonator fig. 47 external circuit of rc oscillation x i n c o u t c in x o u t m 3 7 5 4 0 r d x i n x o u t c r m 3 7 5 4 0 fig. 48 external clock input circuit x in x o u t e x t e r n a l o s c i l l a t i o n c i r c u i t v cc v ss o p e n m37540 x i n x o u t m 3 7 5 4 0 open fig. 49 processing of x in and x out pins at ring oscillator op- eration clock generating circuit an oscillation circuit can be formed by connecting a resonator be- tween x in and x out , and an rc oscillation circuit can be formed by connecting a resistor and a capacitor. use the circuit constants in accordance with the resonator manufacturer's recommended values. (1) ring oscillator operation when the mcu operates by the ring oscillator for the main clock, connect x in pin to v ss and leave x out pin open. the clock frequency of the ring oscillator depends on the supply voltage and the operation temperature range. be careful that variable frequencies when designing application products. (2) ceramic resonator when the ceramic resonator is used for the main clock, connect the ceramic resonator and the external circuit to pins x in and x out at the shortest distance. a feedback resistor is built in be- tween pins x in and x out . (3) rc oscillation when the rc oscillation is used for the main clock, connect the x in pin to the external circuit of resistor r and the capacitor c at the shortest distance and leave x out pin open. the frequency is affected by a capacitor, a resistor and a micro- computer. so, set the constants within the range of the frequency limits. (4) external clock when the external signal clock is used for the main clock, connect the x in pin to the clock source and leave x out pin open. externally connect a damping resistor rd de- pending on the oscillation frequency. (a feedback resistor is built-in.) use the resonator manufacturer s recom- mended value because constants such as ca- pacitance depend on the resonator. note: connect the external circuit of resistor r and the capacitor c at the shortest distance. the frequency is af- fected by a capacitor, a resistor and a micro- computer. so, set the constants within the range of the frequency limits. note: the clock frequency of the ring oscillator depends on the supply voltage and the operation temperature range. be careful that variable fre- quencies and obtain the sufficient margin. note: single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 45 oscillation stop detection circuit (note) the oscillation stop detection circuit is used for reset occurrence when a ceramic resonator or an oscillation circuit stops by discon- nection. when internal reset occurs, reset because of oscillation stop can be detected by setting ??to the oscillation stop detection status bit. also, when using the oscillation stop detection circuit, a built-in ring oscillator is required. figure 53 shows the state transition. note: the oscillation stop detection circuit is not included in the emulator mcu ?37540rss? fig. 50 structure of misrg misrg(address 0038 16 , initial value: 00 16 ) b7 b0 oscillation stabilization time set bit after release of the stp instruction 0: set 01 16 in timer1, and ff 16 in prescaler 1 automatically 1: not set automatically ceramic or rc oscillation stop detection function active bit 0: detection function inactive 1: detection function active reserved bits (return 0 when read) (do not write 1 to these bits) not used (return 0 when read) oscillation stop detection status bit 0: oscillation stop not detected 1: oscillation stop detected (1) oscillation control ?stop mode when the stp instruction is executed, the internal clock h level and the x in oscillator stops. at this time, timer 1 is set to 01 16 and prescaler 1 is set to ff 16 when the oscillation sta- bilization time set bit after release of the stp instruction is 0 . on the other hand, timer 1 and prescaler 1 are not set when the above bit is 1 . accordingly, set the wait time fit for the oscillation stabilization time of the oscillator to be used. f(x in )/16 is forcibly connected to the input of prescaler 1. when an external interrupt is accepted, oscillation is restarted but the internal clock h until timer 1 underflows. as soon as timer 1 underflows, the internal clock l level to the reset pin while oscillation becomes stable. also, the stp instruction cannot be used while cpu is operating by a ring oscillator. ?wait mode if the wit instruction is executed, the internal clock h level, but the oscillator does not stop. the internal clock re- starts if a reset occurs or when an interrupt is received. since the oscillator does not stop, normal operation can be started immedi- ately after the clock is restarted. to ensure that interrupts will be received to release the stp or wit state, interrupt enable bits must be set to 1 before the stp or wit instruction is executed. notes on clock generating circuit for use with the oscillation stabilization set bit after release of the stp instruction set to 1 , set values in timer 1 and prescaler 1 af- ter fully appreciating the oscillation stabilization time of the oscillator to be used. switch of ceramic and rc oscillations after releasing reset the operation starts by starting a built-in ring oscillator. then, a ceramic oscillation or an rc oscillation is se- lected by setting bit 5 of the cpu mode register. double-speed mode when a ceramic oscillation is selected, a double-speed mode can be used. do not use it when an rc oscillation is selected. cpu mode register bits 5, 1 and 0 of cpu mode register are used to select oscillation mode and to control operation modes of the microcomputer. in or- der to prevent the dead-lock by error-writing (ex. program run-away), these bits can be rewritten only once after releasing re- set. after rewriting it is disable to write any data to the bit. (the emulator mcu m37540rss is excluded.) also, when the read-modify-write instructions (seb, clb) are ex- ecuted to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked. clock division ratio, x in oscillation control, ring oscillator control the state transition shown in fig. 52 can be performed by setting the clock division ratio selection bits (bits 7 and 6), x in oscillation control bit (bit 4), ring oscillator oscillation control bit (bit 3) of cpu mode register. be careful of notes on use in fig. 52. single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 46 fig. 51 block diagram of internal clock generating circuit (for ceramic resonator) fig. 52 block diagram of internal clock generating circuit (for rc oscillation) s r q s r q 1 / 2 r s q r f 1/4 1/2 wit instruction stp instruction timing (internal clock) s t p i n s t r u c t i o n interrupt request reset interrupt disable flag l high-speed mode m i d d l e - s p e e d m o d e p r e s c a l e r 1 t i m e r 1 main clock division ratio selection bit double-speed mode ring oscillator mode r i n g o s c i l l a t o r r i n g x o u t x i n 1 / 8 m a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t m i d d l e - , h i g h - , l o w - s p e e d m o d e r i n g o s c i l l a t o r m o d e r e s e t s r q s r q 1 / 2 r s q 1/4 1 / 2 w i t i n s t r u c t i o n stp instruction t i m i n g ( i n t e r n a l c l o c k ) stp instruction i n t e r r u p t r e q u e s t r e s e t interrupt disable flag l h i g h - s p e e d m o d e m i d d l e - s p e e d m o d e p r e s c a l e r 1 timer 1 main clock division ratio selection bit d o u b l e - s p e e d m o d e r i n g o s c i l l a t o r m o d e r i n g o s c i l l a t o r r i n g x o u t x i n d e l a y 1 / 8 main clock division ratio selection bit middle-, high-, low-speed mode r i n g o s c i l l a t o r m o d e r e s e t single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 47 fig. 53 state transition s t o p m o d e wait mode w i t i n s t r u c t i o n o s c i l l a t i o n s t o p d e t e c t i o n c i r c u i t v a l i d c p u m 4 1 2 misrg 1 1 2 i n t e r r u p t i n t e r r u p t stp instruction wit instruction i n t e r r u p t misrg 1 0 2 c p u m 3 1 2 c p u m 3 0 2 c p u m 7 6 1 0 2 c p u m 7 6 0 0 2 0 1 2 1 1 2 ( n o t e 2 ) c p u m 4 0 2 misrg 1 1 2 misrg 1 0 2 reset released s t a t e 1 o p e r a t i o n c l o c k s o u r c e : f (x i n ) ( n o t e 1 ) f (x i n ) o s c i l l a t i o n e n a b l e d r i n g o s c i l l a t o r s t o p state 2 operation clock source: f(x in ) (note 1) f(x in ) oscillation enabled ring oscillator enabled state 3 operation clock source: ring oscillator (note 3) f(x in ) oscillation enabled ring oscillator enalbed s t a t e 4 o p e r a t i o n c l o c k s o u r c e : r i n g o s c i l l a t o r ( n o t e 3 ) f (x i n ) o s c i l l a t i o n s t o p r i n g o s c i l l a t o r e n a l b e d n o t e s o n s w i t c h o f c l o c k ( 1 ) i n o p e r a t i o n c l o c k s o u r c e = f (x i n ) , t h e f o l l o w i n g c a n b e s e l e c t e d f o r t h e c p u c l o c k d i v i s i o n r a t i o . f ( x i n ) / 2 ( h i g h - s p e e d m o d e ) f ( x i n ) / 8 ( m i d d l e - s p e e d m o d e ) f ( x i n ) ( d o u b l e - s p e e d m o d e , o n l y a t a c e r a m i c o s c i l l a t i o n ) ( 2 ) e x e c u t e t h e s t a t e t r a n s i t i o n s t a t e 3 t o s t a t e 2 o r s t a t e 3 t o s t a t e 2 a f t e r s t a b i l i z i n g x i n o s c i l l a t i o n . ( 3 ) i n o p e r a t i o n c l o c k s o u r c e = r i n g o s c i l l a t o r , t h e m i d d l e - s p e e d m o d e i s s e l e c t e d f o r t h e c p u c l o c k d i v i s i o n r a t i o . ( 4 ) w h e n t h e s t a t e t r a n s i t i o n s t a t e 2 s t a t e 3 s t a t e 4 i s p e r f o r m e d , e x e c u t e t h e n o p i n s t r u c t i o n a s s h o w n b e l o w a c c o r d i n g t o t h e d i v i s i o n r a t i o o f c p u c l o c k . c p u m 7 6 1 0 2 ( s t a t e 2 s t a t e 3 ) n o p i n s t r u c t i o n c p u m 4 1 2 ( s t a t e 3 s t a t e 4 ) d o u b l e - s p e e d m o d e a t r i n g o s c i l l a t o r : n o p ? 3 h i g h - s p e e d m o d e a t r i n g o s c i l l a t o r : n o p ? 1 m i d d l e - s p e e d m o d e a t r i n g o s c i l l a t o r : n o p ? 0 reset state cpum 76 10 2 cpum 76 00 2 01 2 11 2 (note 2) s t a t e 2 o p e r a t i o n c l o c k s o u r c e : f (x i n ) ( n o t e 1 ) f (x i n ) o s c i l l a t i o n e n a b l e d r i n g o s c i l l a t o r e n a b l e d s t a t e 3 o p e r a t i o n c l o c k s o u r c e : r i n g o s c i l l a t o r ( n o t e 3 ) f ( x i n ) o s c i l l a t i o n e n a b l e d r i n g o s c i l l a t o r e n a l b e d single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 48 notes on programming processor status register the contents of the processor status register (ps) after reset are undefined except for the interrupt disable flag i which is ?? after reset, initialize flags which affect program execution. in particular, it is essential to initialize the t flag and the d flag because of their effect on calculations. interrupts the contents of the interrupt request bit do not change even if the bbc or bbs instruction is executed immediately after they are changed by program because this instruction is executed for the previous contents. for executing the instruction for the changed contents, execute one instruction before executing the bbc or bbs instruction. decimal calculations ?for calculations in decimal notation, set the decimal mode flag d to ?? then execute the adc instruction or sbc instruction. in this case, execute sec instruction, clc instruction or cld in- struction after executing one instruction before the adc instruction or sbc instruction. ?in the decimal mode, the values of the n (negative), v (overflow) and z (zero) flags are invalid. ports ?the values of the port direction registers cannot be read. that is, it is impossible to use the lda instruction, memory opera- tion instruction when the t flag is ?? addressing mode using direction register values as qualifiers, and bit test instructions such as bbc and bbs. it is also impossible to use bit operation instructions such as clb and seb and read/modify/write instructions of direction registers for calculations such as ror. for setting direction registers, use the ldm instruction, sta in- struction, etc. a-d conversion do not execute the stp instruction during a-d conversion. instruction execution timing the instruction execution time can be obtained by multiplying the frequency of the internal clock by the number of cycles men- tioned in the machine-language instruction table. the frequency of the internal clock is the same as that of the x in in double-speed mode, twice the x in cycle in high-speed mode and 8 times the x in cycle in middle-speed mode. cpu mode register the oscillation mode selection bit and processor mode bits can be rewritten only once after releasing reset. however, after rewriting it is disable to write any value to the bit. (emulator mcu is ex- cluded.) when a ceramic oscillation is selected, a double-speed mode of the clock division ratio selection bits can be used. do not use it when an rc oscillation is selected. state transition do not stop the clock selected as the operation clock because of setting of cm3, 4. notes on hardware handling of power source pin in order to avoid a latch-up occurrence, connect a capacitor suit- able for high frequencies as bypass capacitor between power source pin (vcc pin) and gnd pin (vss pin). besides, connect the capacitor to as close as possible. for bypass capacitor which should not be located too far from the pins to be connected, a ce- ramic capacitor of 0.01 f to 0.1 f is recommended. one time prom version the cnvss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (v pp pin) as well. to improve the noise reduction, connect a track between cnvss pin and vss pin with 1 to 10 k ? resistance. the mask rom version track of cnvss pin has no operational in- terference even if it is connected via a resistor. single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 49 notes on peripheral functions interrupt when setting the followings, the interrupt request bit may be set to 1 . when setting external interrupt active edge related register: interrupt edge selection register (address 003a 16 ) timer x mode register (address 2b 16 ) timer a mode register (address 1d 16 ) when not requiring the interrupt occurrence synchronized with these setting, take the following sequence. ? set the corresponding interrupt enable bit to 0 (disabled). ? set the interrupt edge select bit (active edge switch bit) to 1 . ? set the corresponding interrupt request bit to 0 after 1 or more instructions have been executed. ? set the corresponding interrupt enable bit to 1 (enabled). timers when n (0 to 255) is written to a timer latch, the frequency divi- sion ratio is 1/(n+1). when a count source of timer x, timer y or timer z is switched, stop a count of timer x. timer a cntr 1 interrupt active edge selection cntr 1 interrupt active edge depends on the cntr 1 active edge switch bit. when this bit is 0 , the cntr 1 interrupt request bit is set to 1 at the falling edge of the cntr 1 pin input signal. when this bit is 1 , the cntr 1 interrupt request bit is set to 1 at the rising edge of the cntr 1 pin input signal. however, in the pulse width hl continuously measurement mode, cntr 1 interrupt request is generated at both rising and falling edges of cntr 1 pin input signal regardless of the setting of cntr 1 active edge switch bit. timer x cntr 0 interrupt active edge selection cntr 0 interrupt active edge depends on the cntr 0 active edge switch bit. when this bit is 0 , the cntr 0 interrupt request bit is set to 1 at the falling edge of cntr 0 pin input signal. when this bit is 1 , the cntr 0 interrupt request bit is set to 1 at the rising edge of cntr 0 pin input signal. timer y: programmable generation waveform mode count set value in the programmable waveform generation mode, values of tys, expyp, and expys are valid by writing to typ because the set- ting to them is executed all at once by writing to typ. even when changing typ is not required, write the same value again. write timing to typ in the programmable waveform generation mode, when the set- ting value is changed while the waveform is output, set by software in order not to execute the writing to typ and the timing of timer underflow during the secondary interval simultanesously. usage of waveform extension function the waveform extension function by the timer y waveform exten- sion control bit can be used only when 00 16 is set to prescaler y. when the value other than 00 16 is set to prescaler y, be sure to set 0 to expyp and expys. timer y write mode when using this mode, be sure to set 1 to the timer y write con- trol bit to select write to latch only . timer y can stop counting by setting 1 to the timer y count stop bit in any mode. also, when timer y underflows, the timer y interrupt request bit is set to 1 . timer y reloads the value of latch when counting is stopped by the timer y count stop bit. (when timer is read out while timer is stopped, the value of latch is read. the value of timer can be read out only while timer is operating.) timer z: programmable waveform generation mode count set value in the programmable waveform generation mode, values of tzs, expzp, and expzs are valid by writing to tzp because the set- ting to them is executed all at once by writing to tzp. even when changing tzp is not required, write the same value again. write timing to tzp in the programmable waveform generation mode, when the set- ting value is changed while the waveform is output, set by software in order not to execute the writing to tzp and the timing of timer underflow during the secondary interval simultanesously. usage of waveform extension function the waveform extension function by the timer z waveform exten- sion control bit can be used only when 00 16 is set to prescaler z. when the value other than 00 16 is set to prescaler z, be sure to set 0 to expzp and expzs. also, when the timer y underflow is selected as the count source, the waveform extension function cannot be used. timer z write mode when using this mode, be sure to set 1 to the timer z write con- trol bit to select write to latch only . single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 50 timer z: programmable one-shot generation mode count set value in the programmable one-shot generation mode, the value of expzp becomes valid by writing to tzp. even when changing tzp is not required, write the same value again. write timing to tzp in the programmable one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to tzp and the timing of timer un- derflow simultanesously. usage of waveform extension function the waveform extension function by the timer z waveform exten- sion control bit can be used only when 00 16 is set to prescaler z. when the value other than 00 16 is set to prescaler z, be sure to set 0 to expzp. also, when the timer y underflow is selected as the count source, the waveform extension function cannot be used. timer z write mode when using this mode, be sure to set 1 to the timer z write con- trol bit to select write to latch only . timer z: programmable wait one-shot generation mode count set value in the programmable wait one-shot generation mode, values of tzs, expzp and expzs are valid by writing to tzp. even when changing tzp is not required, write the same value again. write timing to tzp in the programmable wait one-shot generation mode, when the setting value is changed while the waveform is output, set by soft- ware in order not to execute the writing to tzp and the timing of timer underflow during the secondary interval simultanesously. usage of waveform extension function the waveform extension function by the timer z waveform exten- sion control bit can be used only when 00 16 is set to prescaler z. when the value other than 00 16 is set to prescaler z, be sure to set 0 to expzp and expzs. also, when the timer y underflow is selected as the count source, the waveform extension function cannot be used. timer z write mode when using this mode, be sure to set 1 to the timer z write con- trol bit to select write to latch only . timer z can stop counting by setting 1 to the timer z count stop bit in any mode. also, when timer z underflows, the timer z interrupt request bit is set to 1 . timer z reloads the value of latch when counting is stopped by the timer z count stop bit. (when timer is read out while timer is stopped, the value of latch is read. the value of timer can be read out only while timer is operating.) serial i/o serial i/o interrupt when setting the transmit enable bit to 1 , the serial i/o transmit interrupt request bit is automatically set to 1 . when not requiring the interrupt occurrence synchronized with the transmission en- abled, take the following sequence. ? set the serial i/o transmit interrupt enable bit to 0 (disabled). ? set the transmit enable bit to 1 . ? set the serial i/o transmit interrupt request bit to 0 after 1 or more instructions have been executed. ? set the serial i/o transmit interrupt enable bit to 1 (enabled). i/o pin function when serial i/o1 is enabled. the functions of p1 2 and p1 3 are switched with the setting values of a serial i/o1 mode selection bit and a serial i/o1 synchronous clock selection bit as follows. (1) serial i/o1 mode selection bit 1 : clock synchronous type serial i/o is selected. setup of a serial i/o1 synchronous clock selection bit 0 : p1 2 pin turns into an output pin of a synchronous clock. 1 : p1 2 pin turns into an input pin of a synchronous clock. setup of a srdy1 output enable bit (srdy) 0 : p1 3 pin can be used as a normal i/o pin. 1 : p1 3 pin turns into a srdy output pin. (2) serial i/o1 mode selection bit 0 : clock asynchronous (uart) type serial i/o is selected. setup of a serial i/o1 synchronous clock selection bit 0 : p1 2 pin can be used as a normal i/o pin. 1 : p1 2 pin turns into an input pin of an external clock. when clock asynchronous (uart) type serial i/o is selected, it is p1 3 pin. it can be used as a normal i/o pin. a-d converter the comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. make sure that f(x in ) is 500khz or more during a-d conversion. single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 51 data required for mask orders the following are necessary when ordering a mask rom produc- tion: 1.mask rom order confirmation form * 2.mark specification form * 3.data to be written to rom, in eprom form (three identical cop- ies) or one floppy disk. data required for rom programming orders the following are necessary when ordering a one time prom production: 1.rom programming order confirmation form * 2.mark specification form * 3.data to be written to rom, in eprom form (three identical cop- ies) or one floppy disk. * for the mask rom confirmation, rom programming order con- firmation and the mark specifications, refer to the mitsubishi mcu technical information homepage (http://www.infomicom.maec.co.jp/indexe.htm). rom programming method the built-in prom of the blank one time prom version can be read or programmed with a general-purpose prom programmer using a special programming adapter. set the address of prom programmer in the user rom area. the prom of the blank one time prom version is not tested or screened in the assembly process and following processes. to en- sure proper operation after programming, the procedure shown in figure 54 is recommended to verify programming. package 32p4b 32p6u-a 36p2r-a name of programming adapter pca7435spg02 pca7435gpg03 pca7435fpg02 table 7 special programming adapter fig. 54 programming and testing of one time prom version programming with prom programmer screening (caution) (150 c for 40 hours) verification with prom programmer functional check in target device the screening temperature is far higher than the storage temperature. never expose to 150 c exceeding 100 hours. caution: single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 52 electrical characteristics 1.7540group (general purpose) applied to: m37540m2-xxxfp/sp/gp, M37540M4-XXXFP/sp/gp, m37540e2fp/sp/gp, m37540e8fp/sp/gp absolute maximum ratings (general purpose) table 8 absolute maximum ratings ?.3 to 6.5 ( note 1 ) ?.3 to v cc + 0.3 ?.3 to v cc + 0.3 ?.3 to 13 ?.3 to v cc + 0.3 300 ( note 3 ) ?0 to 85 ?0 to 125 power source voltage input voltage p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 0 ?3 7 , v ref input voltage reset, x in input voltage cnv ss ( note 2 ) output voltage p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 0 ?3 7 , x out power dissipation operating temperature storage temperature v v v v v mw ? ? v cc v i v i v i v o p d t opr t stg conditions symbol ratings unit parameter all voltages are based on v ss . output transistors are cut off. ta = 25? notes 1: this is the rating value for the mask rom version. the rating value for the one time prom version is ?.3 to 7.0 v. 2: it is a rating only for the one time prom version. connect to v ss for the mask rom version. 3: 200 mw for the 32p6u package product. single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 53 recommended operating conditions (general purpose) table 9 recommended operating conditions (1) (v cc = 2.2 to 5.5 v, ta = ?0 to 85 ?, unless otherwise noted) 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 v cc v cc 4.0 2.4 2.2 4.5 4.0 2.4 2.2 4.0 2.4 2.2 2.0 0.8v cc 2.0 0.8v cc 0 0 0 0 min. typ. max. symbol parameter unit power source voltage (ceramic) f(x in ) = 8 mhz (high-, middle-speed mode) f(x in ) = 4 mhz (high-, middle-speed mode) f(x in ) = 2 mhz (high-, middle-speed mode) f(x in ) = 6 mhz (double-speed mode) f(x in ) = 4 mhz (double-speed mode) f(x in ) = 2 mhz (double-speed mode) f(x in ) = 1 mhz (double-speed mode) f(x in ) = 4 mhz (high-, middle-speed mode) f(x in ) = 2 mhz (high-, middle-speed mode) f(x in ) = 1 mhz (high-, middle-speed mode) 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 0 limits v cc v v v v v v v v v v v v v v v v v v v ma ma ma ma ma ma power source voltage analog reference voltage ??input voltage p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 0 ?3 7 ??input voltage (ttl input level selected) p1 0 , p1 2 , p1 3 , p3 6 , p3 7 (note 1) ??input voltage reset, x in ??input voltage p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 0 ?3 7 ??input voltage (ttl input level selected) p1 0 , p1 2 , p1 3 , p3 6 , p3 7 (note 1) ??input voltage reset, cnv ss ??input voltage x in ??total peak output current (note 2) p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 0 ?3 7 ??total peak output current (note 2) p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 7 ??total peak output current (note 2) p3 0 ?3 6 ??total average output current (note 2) p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 0 ?3 7 ??total average output current (note 2) p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 7 ??total average output current (note 2) p3 0 ?3 6 note 1: vcc = 4.0 to 5.5v 2: the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an average value measured over 100 ms. the total peak current is the peak value of all the currents. v cc v cc 0.3v cc 0.8 0.2v cc 0.16v cc ?0 80 60 ?0 40 30 v ss v ref v ih v ih v ih v il v il v il v il i oh(peak) i ol(peak) i ol(peak) i oh(avg) i ol(avg) i ol(avg) power source voltage (rc) single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 54 recommended operating conditions (general purpose)(continued) table 10 recommended operating conditions (2) (v cc = 2.2 to 5.5 v, ta = ?0 to 85 ?, unless otherwise noted) ??peak output current (note 1) p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 0 ?3 7 ??peak output current (note 1) p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 7 ??peak output current (note 1) p3 0 ?3 6 ??average output current (note 2) p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 0 ?3 7 ??average output current (note 2) p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 7 ??average output current (note 2) p3 0 ?3 6 internal clock oscillation frequency (note 3) v cc = 4.5 to 5.5 v at ceramic oscillation or external clock input double-speed mode internal clock oscillation frequency (note 3) v cc = 4.0 to 5.5 v at ceramic oscillation or external clock input double-speed mode internal clock oscillation frequency (note 3) v cc = 2.4 to 5.5 v at ceramic oscillation or external clock input double-speed mode internal clock oscillation frequency (note 3) v cc = 2.2 to 5.5 v at ceramic oscillation or external clock input double-speed mode internal clock oscillation frequency (note 3) v cc = 4.0 to 5.5 v at ceramic oscillation or external clock input high-, middle-speed mode internal clock oscillation frequency (note 3) v cc = 2.4 to 5.5 v at ceramic oscillation or external clock input high-, middle-speed mode internal clock oscillation frequency (note 3) v cc = 2.2 to 5.5 v at ceramic oscillation or external clock input high-, middle-speed mode internal clock oscillation frequency (note 3) v cc = 4.0 to 5.5 v at rc oscillation high-, middle-speed mode internal clock oscillation frequency (note 3) v cc = 2.4 to 5.5 v at rc oscillation high-, middle-speed mode internal clock oscillation frequency (note 3) v cc = 2.2 to 5.5 v at rc oscillation high-, middle-speed mode symbol parameter limits max. typ. min. ?0 10 30 ? 5 15 6 4 2 1 8 4 2 4 2 1 notes 1: the peak output current is the peak current flowing in each port. 2: the average output current i ol (avg), i oh (avg) in an average value measured over 100 ms. 3: when the oscillation frequency has a duty cycle of 50 %. i oh(peak) i ol(peak) i ol(peak) i oh(avg) i ol(avg) i ol(avg) f(x in ) ma ma ma ma ma ma mhz mhz mhz mhz mhz mhz mhz mhz mhz mhz unit single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 55 electrical characteristics (general purpose) table 11 electrical characteristics (1) (v cc = 2.2 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit i oh = ? ma v cc = 4.0 to 5.5 v i oh = ?.0 ma v cc = 2.2 to 5.5 v i ol = 5 ma v cc = 4.0 to 5.5 v i ol = 1.5 ma v cc = 4.0 to 5.5 v i ol = 1.0 ma v cc = 2.2 to 5.5 v i ol = 15 ma v cc = 4.0 to 5.5 v i ol = 1.5 ma v cc = 4.0 to 5.5 v i ol = 10 ma v cc = 2.2 to 5.5 v v i = v cc (pin floating. pull up transistors ?ff? v i = v cc v i = v cc v i = v ss (pin floating. pull up transistors ?ff? v i = v ss v i = v ss v i = v ss (pull up transistors ?n? when clock stopped v cc = 5.0 v, ta = 25 ? v cc = 5.0 v, ta = 25 ? test conditions v cc ?.5 v cc ?.0 2.0 1000 62.5 ??output voltage p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 0 ?3 7 (note 1) ??output voltage p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 7 ??output voltage p3 0 ?3 6 hysteresis cntr 0 , cntr 1 , int 0 , int 1 (note 2) p0 0 ?0 7 (note 3) hysteresis r x d, s clk1 , s clk2 , s data2 (note 2) hysteresis reset ??input current p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 0 ?3 7 ??input current reset ??input current x in ??input current p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 0 ?3 7 ??input current reset, cnv ss ??input current x in ??input current p0 0 ?0 7 , p3 0 ?3 7 ram hold voltage ring oscillator oscillation frequency oscillation stop detection circuit detection frequency 1.5 0.3 1.0 2.0 0.3 1.0 5.0 5.0 ?.0 ?.0 ?.5 5.5 3000 187.5 v v v v v v v v v v v a a a a a a ma v khz khz v oh v ol v ol v t+ ? t v t+ ? t v t+ ? t i ih i ih i ih i il i il i il i il v ram r osc d osc 0.4 0.5 0.5 4.0 ?.0 ?.2 2000 125 notes 1: p1 1 is measured when the p1 1 /t x d 1 p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is ?? 2: r x d 1 , s clk1 , s clk2 , s data2 , int 0 , and int 1 have hysteresises only when bits 0 to 2 of the port p1p3 control register are set to ??(cmos level). 3: it is available only when operating key-on wake up. single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 56 electrical characteristics (general purpose)(continued) table 12 electrical characteristics (2) (v cc = 2.2 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit test conditions power source current 8.0 1.5 10.0 5.0 1000 3.2 450 1.0 10 6.5 1.2 8.0 5.0 900 3.2 450 1.0 10 ma ma ma ma a ma ma a ma a a ma ma ma ma a ma ma a ma a a i cc 5.0 0.5 6.0 2.0 350 1.6 0.2 150 0.5 0.1 3.5 0.4 4.5 2.0 300 1.6 0.2 150 0.5 0.1 high-speed mode, f(x in ) = 8 mhz output transistors ?ff high-speed mode, f(x in ) = 2 mhz, v cc = 2.2 v output transistors ?ff double-speed mode, f(x in ) = 6 mhz output transistors ?ff middle-speed mode, f(x in ) = 8 mhz output transistors ?ff ring oscillator operation mode, v cc = 5 v output transistors ?ff f(x in ) = 8 mhz (in wit state), functions except timer 1 disabled, output transistors ?ff f(x in ) = 2 mhz, v cc = 2.2 v (in wit state), functions except timer 1 disabled, output transistors ?ff ring oscillator operation mode, v cc = 5v output transistors ?ff increment when a-d conversion is executed f(x in ) = 8 mhz, v cc = 5 v all oscillation stopped (in stp state) output transistors ?ff high-speed mode, f(x in ) = 8 mhz output transistors ?ff high-speed mode, f(x in ) = 2 mhz, v cc = 2.2 v output transistors ?ff double-speed mode, f(x in ) = 6 mhz output transistors ?ff middle-speed mode, f(x in ) = 8 mhz output transistors ?ff ring oscillator operation mode, v cc = 5 v output transistors ?ff f(x in ) = 8 mhz (in wit state), functions except timer 1 disabled, output transistors ?ff f(x in ) = 2 mhz, v cc = 2.2 v (in wit state), functions except timer 1 disabled, output transistors ?ff ring oscillator operation mode, v cc = 5v output transistors ?ff increment when a-d conversion is executed f(x in ) = 8 mhz, v cc = 5 v all oscillation stopped (in stp state) output transistors ?ff one time prom version mask rom version ta = 25 ? ta = 85 ? ta = 25 ? ta = 85 ? single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 57 a-d converter characteristics (general purpose) table 13 a-d converter characteristics (v cc = 2.7 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) resolution linearity error differential nonlinear error zero transition voltage full scale transition voltage conversion time ladder resistor reference power source input current a-d port input current resolution linearity error differential nonlinear error zero transition voltage full scale transition voltage conversion time ladder resistor reference power source input current a-d port input current min. typ. max. symbol parameter limits unit test conditions v cc = 2.7 to 5.5 v ta = 25 ? v cc = 2.7 to 5.5 v ta = 25 ? v cc = v ref = 5.12 v v cc = v ref = 3.072 v v cc = v ref = 5.12 v v cc = v ref = 3.072 v v ref = 5.0 v v ref = 3.0 v v cc = 2.7 to 5.5 v ta = 25 ? v cc = 2.7 to 5.5 v ta = 25 ? v cc = v ref = 5.12 v v cc = v ref = 3.072 v v cc = v ref = 5.12 v v cc = v ref = 3.072 v v ref = 5.0 v v ref = 3.0 v bits lsb lsb mv mv mv mv tc(x in ) k ? a a bits lsb lsb mv mv mv mv tc(x in ) k ? a a 10 ? ?.9 20 15 5125 3075 122 200 120 5.0 10 ? ?.5 35 21 5150 3090 122 200 120 5.0 v ot v fst t conv r ladder i vref i i(ad) v ot v fst t conv r ladder i vref i i(ad) 5 3 5115 3069 55 150 70 15 9 5125 3075 55 150 70 0 0 5105 3060 50 50 0 0 5105 3060 50 50 one time prom version mask rom version single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 58 timing requirements (general purpose) table 14 timing requirements (1) (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit reset input ??pulse width external clock input cycle time external clock input ??pulse width external clock input ??pulse width cntr 0 input cycle time cntr 0 , int 0 , int 1 , input ??pulse width cntr 0 , int 0 , int 1 , input ??pulse width cntr 1 input cycle time cntr 1 input ??pulse width cntr 1 input ??pulse width serial i/o1 clock input cycle time (note) serial i/o1 clock input ??pulse width (note) serial i/o1 clock input ??pulse width (note) serial i/o1 input set up time serial i/o1 input hold time serial i/o2 clock input cycle time serial i/o2 clock input ??pulse width serial i/o2 clock input ??pulse width serial i/o2 input set up time serial i/o2 input hold time t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr 0 ) t wh (cntr 0 ) t wl (cntr 0 ) t c (cntr 1 ) t wh (cntr 1 ) t wl (cntr 1 ) t c (s clk1 ) t wh (s clk1 ) t wl (s clk1 ) t su (rxd 1 ? clk1 ) t h (s clk1 ?xd 1 ) t c (s clk2 ) t wh (s clk2 ) t wl (s clk2 ) t su (s data2 ? clk2 ) t h (s clk2 ? data2 ) 2 125 50 50 200 80 80 2000 800 800 800 370 370 220 100 1000 400 400 200 200 s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns note: in this time, bit 6 of the serial i/o1 control register (address 001a 16 ) is set to ??(clock synchronous serial i/o1 is selected). when bit 6 of the serial i/o1 control register is ??(clock asynchronous serial i/o1 is selected), the rating values are divid ed by 4. table 15 timing requirements (2) (v cc = 2.4 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit reset input ??pulse width external clock input cycle time external clock input ??pulse width external clock input ??pulse width cntr 0 input cycle time cntr 0 , int 0 , int 1 , input ??pulse width cntr 0 , int 0 , int 1 , input ??pulse width cntr 1 input cycle time cntr 1 input ??pulse width cntr 1 input ??pulse width serial i/o1 clock input cycle time (note) serial i/o1 clock input ??pulse width (note) serial i/o1 clock input ??pulse width (note) serial i/o1 input set up time serial i/o1 input hold time serial i/o2 clock input cycle time serial i/o2 clock input ??pulse width serial i/o2 clock input ??pulse width serial i/o2 input set up time serial i/o2 input hold time t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr 0 ) t wh (cntr 0 ) t wl (cntr 0 ) t c (cntr 1 ) t wh (cntr 1 ) t wl (cntr 1 ) t c (s clk1 ) t wh (s clk1 ) t wl (s clk1 ) t su (rxd 1 ? clk1 ) t h (s clk1 ?xd 1 ) t c (s clk2 ) t wh (s clk2 ) t wl (s clk2 ) t su (s data2 ? clk2 ) t h (s clk2 ? data2 ) 2 250 100 100 500 230 230 4000 1600 1600 2000 950 950 400 200 2000 950 950 400 400 s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns note: in this time, bit 6 of the serial i/o1 control register (address 001a 16 ) is set to ??(clock synchronous serial i/o1 is selected). when bit 6 of the serial i/o1 control register is ??(clock asynchronous serial i/o1 is selected), the rating values are divid ed by 4. single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 59 table 16 timing requirements (3) (v cc = 2.2 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit reset input ??pulse width external clock input cycle time external clock input ??pulse width external clock input ??pulse width cntr 0 input cycle time cntr 0 , int 0 , int 1 , input ??pulse width cntr 0 , int 0 , int 1 , input ??pulse width cntr 1 input cycle time cntr 1 input ??pulse width cntr 1 input ??pulse width serial i/o1 clock input cycle time (note) serial i/o1 clock input ??pulse width (note) serial i/o1 clock input ??pulse width (note) serial i/o1 input set up time serial i/o1 input hold time serial i/o2 clock input cycle time serial i/o2 clock input ??pulse width serial i/o2 clock input ??pulse width serial i/o2 input set up time serial i/o2 input hold time t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr 0 ) t wh (cntr 0 ) t wl (cntr 0 ) t c (cntr 1 ) t wh (cntr 1 ) t wl (cntr 1 ) t c (s clk1 ) t wh (s clk1 ) t wl (s clk1 ) t su (rxd 1 ? clk1 ) t h (s clk1 ?xd 1 ) t c (s clk2 ) t wh (s clk2 ) t wl (s clk2 ) t su (s data2 ? clk2 ) t h (s clk2 ? data2 ) 2 500 200 200 1000 460 460 8000 3200 3200 4000 1900 1900 800 400 4000 1900 1900 800 800 s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns note: in this time, bit 6 of the serial i/o1 control register (address 001a 16 ) is set to ??(clock synchronous serial i/o1 is selected). when bit 6 of the serial i/o1 control register is ??(clock asynchronous serial i/o1 is selected), the rating values are divid ed by 4. single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 60 switching characteristics (general purpose) table 17 switching characteristics (1) (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) t c (s clk1 )/2?0 t c (s clk1 )/2?0 ?0 t c (s clk2 )/2?0 t c (s clk2 )/2?0 0 min. typ. max. symbol parameter limits unit t wh (s clk1 ) t wl (s clk1 ) t d (s clk1 ?xd 1 ) t v (s clk1 ?xd 1 ) t r (s clk1 ) t f (s clk1 ) t wh (s clk2 ) t wl (s clk2 ) t d (s clk2 ? data2 ) t v (s clk2 ? data2 ) t r (s clk2 ) t f (s clk2 ) t r (cmos) t f (cmos) serial i/o1 clock output ??pulse width serial i/o1 clock output ??pulse width serial i/o1 output delay time serial i/o1 output valid time serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output ??pulse width serial i/o2 clock output ??pulse width serial i/o2 output delay time serial i/o2 output valid time serial i/o2 clock output rising time serial i/o2 clock output falling time cmos output rising time (note 1) cmos output falling time (note 1) note 1: pin x out is excluded. table 18 switching characteristics (2) (v cc = 2.4 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit 350 50 50 350 50 50 50 50 note 1: pin x out is excluded. t wh (s clk1 ) t wl (s clk1 ) t d (s clk1 ? x d 1 ) t v (s clk1 ? x d 1 ) t r (s clk1 ) t f (s clk1 ) t wh (s clk2 ) t wl (s clk2 ) t d (s clk2 ? data2 ) t v (s clk2 ? data2 ) t r (s clk2 ) t f (s clk2 ) t r (cmos) t f (cmos) serial i/o1 clock output ??pulse width serial i/o1 clock output ??pulse width serial i/o1 output delay time serial i/o1 output valid time serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output ??pulse width serial i/o2 clock output ??pulse width serial i/o2 output delay time serial i/o2 output valid time serial i/o2 clock output rising time serial i/o2 clock output falling time cmos output rising time (note 1) cmos output falling time (note 1) t c (s clk1 )/2?0 t c (s clk1 )/2?0 ?0 t c (s clk2 )/2?0 t c (s clk2 )/2?0 0 20 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 140 30 30 140 30 30 30 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 61 table 19 switching characteristics (3) (v cc = 2.2 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit 450 70 70 450 70 70 70 70 note 1: pin x out is excluded. switching characteristics measurement circuit diagram (gen- eral purpose) / / / measured output pin cmos output 100 pf t wh (s clk1 ) t wl (s clk1 ) t d (s clk1 ? x d 1 ) t v (s clk1 ? x d 1 ) t r (s clk1 ) t f (s clk1 ) t wh (s clk2 ) t wl (s clk2 ) t d (s clk2 ? data2 ) t v (s clk2 ? data2 ) t r (s clk2 ) t f (s clk2 ) t r (cmos) t f (cmos) serial i/o1 clock output ??pulse width serial i/o1 clock output ??pulse width serial i/o1 output delay time serial i/o1 output valid time serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output ??pulse width serial i/o2 clock output ??pulse width serial i/o2 output delay time serial i/o2 output valid time serial i/o2 clock output rising time serial i/o2 clock output falling time cmos output rising time (note 1) cmos output falling time (note 1) t c (s clk1 )/2?0 t c (s clk1 )/2?0 ?0 t c (s clk2 )/2?0 t c (s clk2 )/2?0 0 25 25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 62 fig. 55 timing chart (general purpose) 0.2v cc t d (s clk1 -txd 1 ) t f 0.2v cc 0.8v cc 0.8v cc t r t su (rxd 1 -s clk1 )t h (s clk1 -rxd 1 ) t v (s clk1 -txd 1 ) t c (s clk1 ) t wl (s clk1 ) t wh (s clk1 ) r x d 1 (at receive) s clk1 0.2v cc t wl (x in ) 0.8v cc t wh (x in ) t c (x in ) x in 0.2v cc 0.8v cc t w (reset) reset 0.2v cc t wl (cntr 0 ) 0.8v cc t wh (cntr 0 ) t c (cntr 0 ) t x d 1 (at transmit) cntr 0 0.2v cc t wl (cntr 0 ) 0.8v cc t wh (cntr 0 ) int 0 , int 1 0.2v cc t wl (cntr 1 ) 0.8v cc t wh (cntr 1 ) t c (cntr 1 ) cntr 1 0.2v cc t d (s clk2 -s data2 ) t f 0.2v cc 0.8v cc 0.8v cc t r t su (s data2 -s clk2 )t h (s clk2 -s data2 ) t v (s clk2 -s data2 ) t c (s clk2 ) t wl (s clk2 ) t wh (s clk2 ) s data2 (at receive) s clk2 s data2 (at transmit) single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 63 electrical characteristics 2.7540group (extended operating temperature version) applied to: m37540m2t-xxxfp/gp, m37540m4t-xxxfp/gp, m37540e8t-xxxfp/gp absolute maximum ratings (extended operating temperature version) table 20 absolute maximum ratings 0.3 to 6.5 ( note 1 ) 0.3 to v cc + 0.3 0.3 to v cc + 0.3 0.3 to v cc + 0.3 300 ( note 2 ) 40 to 85 65 to 150 power source voltage input voltage p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 , v ref input voltage reset, x in , cnv ss output voltage p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 , x out power dissipation operating temperature storage temperature v v v v mw c c v cc v i v i v o p d t opr t stg conditions symbol ratings unit parameter all voltages are based on v ss . output transistors are cut off. ta = 25 c notes 1: this is the rating value for the mask rom version. the rating value for the one time prom version is 0.3 to 7.0 v. 2: 200 mw for the 32p6u package product. single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 64 recommended operating conditions (extended operating temperature version) table 21 recommended operating conditions (1) (v cc = 2.4 to 5.5 v, ta = ?0 to 85 ?, unless otherwise noted) 5.5 5.5 5.5 5.5 5.5 5.5 5.5 v cc v cc v cc v cc 4.0 2.4 4.5 4.0 2.4 4.0 2.4 2.0 0.8v cc 2.0 0.8v cc 0 0 0 0 min. typ. max. symbol parameter unit power source voltage (ceramic) f(x in ) = 8 mhz (high-, middle-speed mode) f(x in ) = 4 mhz (high-, middle-speed mode) f(x in ) = 6 mhz (double-speed mode) f(x in ) = 4 mhz (double-speed mode) f(x in ) = 2 mhz (double-speed mode) f(x in ) = 4 mhz (high-, middle-speed mode) f(x in ) = 2 mhz (high-, middle-speed mode) 5.0 5.0 5.0 5.0 5.0 5.0 5.0 0 limits v cc v v v v v v v v v v v v v v v v ma ma ma ma ma ma power source voltage analog reference voltage h input voltage p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 h input voltage (ttl input level selected) p1 0 , p1 2 , p1 3 , p3 6 , p3 7 (note 1) h input voltage reset, x in l input voltage p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 l input voltage (ttl input level selected) p1 0 , p1 2 , p1 3 , p3 6 , p3 7 (note 1) l input voltage reset, cnv ss l input voltage x in h total peak output current (note 2) p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 l total peak output current (note 2) p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 7 l total peak output current (note 2) p3 0 p3 6 h total average output current (note 2) p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 l total average output current (note 2) p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 7 l total average output current (note 2) p3 0 p3 6 note 1: vcc = 4.0 to 5.5v 2: the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an average value measured over 100 ms. the total peak current is the peak value of all the currents. 0.3v cc 0.8 0.2v cc 0.16v cc 80 80 60 40 40 30 v ss v ref v ih v ih v ih v il v il v il v il i oh(peak) i ol(peak) i ol(peak) i oh(avg) i ol(avg) i ol(avg) power source voltage (rc) single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 65 recommended operating conditions (extended operating temperature version)(continued) table 22 recommended operating conditions (2) (v cc = 2.4 to 5.5 v, ta = ?0 to 85 ?, unless otherwise noted) h peak output current (note 1) p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 l peak output current (note 1) p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 7 l peak output current (note 1) p3 0 p3 6 h average output current (note 2) p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 l average output current (note 2) p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 7 l average output current (note 2) p3 0 p3 6 internal clock oscillation frequency (note 3) v cc = 4.5 to 5.5 v at ceramic oscillation or external clock input double-speed mode internal clock oscillation frequency (note 3) v cc = 4.0 to 5.5 v at ceramic oscillation or external clock input double-speed mode internal clock oscillation frequency (note 3) v cc = 2.4 to 5.5 v at ceramic oscillation or external clock input double-speed mode internal clock oscillation frequency (note 3) v cc = 4.0 to 5.5 v at ceramic oscillation or external clock input high-, middle-speed mode internal clock oscillation frequency (note 3) v cc = 2.4 to 5.5 v at ceramic oscillation or external clock input high-, middle-speed mode internal clock oscillation frequency (note 3) v cc = 4.0 to 5.5 v at rc oscillation high-, middle-speed mode internal clock oscillation frequency (note 3) v cc = 2.4 to 5.5 v at rc oscillation high-, middle-speed mode ma ma ma ma ma ma mhz mhz mhz mhz mhz mhz mhz symbol parameter limits unit max. typ. min. 10 10 30 5 5 15 6 4 2 8 4 4 2 notes 1: the peak output current is the peak current flowing in each port. 2: the average output current i ol (avg), i oh (avg) in an average value measured over 100 ms. 3: when the oscillation frequency has a duty cycle of 50 %. i oh(peak) i ol(peak) i ol(peak) i oh(avg) i ol(avg) i ol(avg) f(x in ) single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 66 electrical characteristics (extended operating temperature version) table 23 electrical characteristics (1) (v cc = 2.4 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit i oh = 5 ma v cc = 4.0 to 5.5 v i oh = 1.0 ma v cc = 2.4 to 5.5 v i ol = 5 ma v cc = 4.0 to 5.5 v i ol = 1.5 ma v cc = 4.0 to 5.5 v i ol = 1.0 ma v cc = 2.4 to 5.5 v i ol = 15 ma v cc = 4.0 to 5.5 v i ol = 1.5 ma v cc = 4.0 to 5.5 v i ol = 10 ma v cc = 2.4 to 5.5 v v i = v cc (pin floating. pull up transistors off ) v i = v cc v i = v cc v i = v ss (pin floating. pull up transistors off ) v i = v ss v i = v ss v i = v ss (pull up transistors on ) when clock stopped v cc = 5.0 v, ta = 25 c v cc = 5.0 v, ta = 25 c test conditions v cc 1.5 v cc 1.0 2.0 1000 62.5 h output voltage p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 (note 1) l output voltage p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 7 l output voltage p3 0 p3 6 hysteresis cntr 0 , cntr 1 , int 0 , int 1 (note 2) p0 0 p0 7 (note 3) hysteresis r x d, s clk1 , s clk2 , s data2 (note 2) hysteresis reset h input current p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 h input current reset h input current x in l input current p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 l input current reset, cnv ss l input current x in l input current p0 0 p0 7 , p3 0 p3 7 ram hold voltage ring oscillator oscillation frequency oscillation stop detection circuit detection frequency 1.5 0.3 1.0 2.0 0.3 1.0 5.0 5.0 5.0 5.0 0.5 5.5 3000 187.5 v v v v v v v v v v v a a a a a a ma v khz khz v oh v ol v ol v t+ v t v t+ v t v t+ v t i ih i ih i ih i il i il i il i il v ram r osc d osc 0.4 0.5 0.5 4.0 4.0 0.2 2000 125 notes 1: p1 1 is measured when the p1 1 /t x d 1 p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0 . 2: r x d1, s clk1 , s clk2 , s data2 , int 0 , and int 1 have hysteresises only when bits 0 to 2 of the port p1p3 control register are set to 0 (cmos level). 3: it is available only when operating key-on wake up. single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 67 electrical characteristics (extended operating temperature version)(continued) table 24 electrical characteristics (2) (v cc = 2.4 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. typ. max. symbol limits unit 8.0 1.5 10.0 5.0 1000 3.2 450 1.0 10 6.5 1.2 8.0 5.0 900 3.2 450 1.0 10 ma ma ma ma a ma ma a ma a a ma ma ma ma a ma ma a ma a a i cc 5.0 0.5 6.0 2.0 350 1.6 0.2 150 0.5 0.1 3.5 0.4 4.5 2.0 300 1.6 0.2 150 0.5 0.1 high-speed mode, f(x in ) = 8 mhz output transistors off high-speed mode, f(x in ) = 2 mhz, v cc = 2.4 v output transistors off double-speed mode, f(x in ) = 6 mhz, output transistors off middle-speed mode, f(x in ) = 8 mhz, output transistors off ring oscillator operation mode, v cc = 5 v output transistors off f(x in ) = 8 mhz (in wit state), functions except timer 1 disabled, output transistors off f(x in ) = 2 mhz, v cc = 2.4 v (in wit state), functions except timer 1 disabled, output transistors off ring oscillator operation mode, v cc = 5v (in wit state), functions except timer 1 disabled, output transistors off increment when a-d conversion is executed f(x in ) = 8 mhz, v cc = 5 v all oscillation stopped (in stp state) output transistors off high-speed mode, f(x in ) = 8 mhz output transistors off high-speed mode, f(x in ) = 2 mhz, v cc = 2.4 v output transistors off double-speed mode, f(x in ) = 6 mhz output transistors off middle-speed mode, f(x in ) = 8 mhz output transistors off ring oscillator operation mode, v cc = 5 v output transistors off f(x in ) = 8 mhz (in wit state), functions except timer 1 disabled, output transistors off f(x in ) = 2 mhz, v cc = 2.4 v (in wit state), functions except timer 1 disabled, output transistors off ring oscillator operation mode, v cc = 5v (in wit state), functions except timer 1 disabled, output transistors off increment when a-d conversion is executed f(x in ) = 8 mhz, v cc = 5 v all oscillation stopped (in stp state) output transistors off ta = 25 c ta = 85 c test conditions one time prom version mask rom version ta = 25 c ta = 85 c single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 68 a-d converter characteristics (extended operating temperature version) table 25 a-d converter characteristics (v cc = 2.7 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) resolution linearity error differential nonlinear error zero transition voltage full scale transition voltage conversion time ladder resistor reference power source input current a-d port input current resolution linearity error differential nonlinear error zero transition voltage full scale transition voltage conversion time ladder resistor reference power source input current a-d port input current min. typ. max. symbol parameter limits unit test conditions v cc = 2.7 to 5.5 v ta = 25 ? v cc = 2.7 to 5.5 v ta = 25 ? v cc = v ref = 5.12 v v cc = v ref = 3.072 v v cc = v ref = 5.12 v v cc = v ref = 3.072 v v ref = 5.0 v v ref = 3.0 v v cc = 2.7 to 5.5 v ta = 25 ? v cc = 2.7 to 5.5 v ta = 25 ? v cc = v ref = 5.12 v v cc = v ref = 3.072 v v cc = v ref = 5.12 v v cc = v ref = 3.072 v v ref = 5.0 v v ref = 3.0 v bits lsb lsb mv mv mv mv tc(x in ) k ? a a bits lsb lsb mv mv mv mv tc(x in ) k ? a a 10 ? ?.9 20 15 5125 3075 122 200 120 5.0 10 ? ?.5 35 21 5150 3090 122 200 120 5.0 v ot v fst t conv r ladder i vref i i(ad) v ot v fst t conv r ladder i vref i i(ad) 5 3 5115 3069 55 150 70 15 9 5125 3075 55 150 70 0 0 5105 3060 50 50 0 0 5105 3060 50 30 one time prom version mask rom version single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 69 timing requirements (extended operating temperature version) table 26 timing requirements (1) (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit reset input l pulse width external clock input cycle time external clock input h pulse width external clock input l pulse width cntr 0 input cycle time cntr 0 , int 0 , int 1 , input h pulse width cntr 0 , int 0 , int 1 , input l pulse width cntr 1 input cycle time cntr 1 input h pulse width cntr 1 input l pulse width serial i/o1 clock input cycle time (note) serial i/o1 clock input h pulse width (note) serial i/o1 clock input l pulse width (note) serial i/o1 input set up time serial i/o1 input hold time serial i/o2 clock input cycle time serial i/o2 clock input h pulse width serial i/o2 clock input l pulse width serial i/o2 input set up time serial i/o2 input hold time t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr 0 ) t wh (cntr 0 ) t wl (cntr 0 ) t c (cntr 1 ) t wh (cntr 1 ) t wl (cntr 1 ) t c (s clk1 ) t wh (s clk1 ) t wl (s clk1 ) t su (rxd 1 s clk1 ) t h (s clk1 rxd 1 ) t c (s clk2 ) t wh (s clk2 ) t wl (s clk2 ) t su (s data2 s clk2 ) t h (s clk2 s data2 ) 2 125 50 50 200 80 80 2000 800 800 800 370 370 220 100 1000 400 400 200 200 s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns note: in this time, bit 6 of the serial i/o1 control register (address 001a 16 ) is set to 1 (clock synchronous serial i/o1 is selected). when bit 6 of the serial i/o1 control register is 0 (clock asynchronous serial i/o1 is selected), the rating values are divided by 4. table 27 timing requirements (2) (v cc = 2.4 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit reset input l pulse width external clock input cycle time external clock input h pulse width external clock input l pulse width cntr 0 input cycle time cntr 0 , int 0 , int 1 , input h pulse width cntr 0 , int 0 , int 1 , input l pulse width cntr 1 input cycle time cntr 1 input h pulse width cntr 1 input l pulse width serial i/o1 clock input cycle time (note) serial i/o1 clock input h pulse width (note) serial i/o1 clock input l pulse width (note) serial i/o1 input set up time serial i/o1 input hold time serial i/o2 clock input cycle time serial i/o2 clock input h pulse width serial i/o2 clock input l pulse width serial i/o2 input set up time serial i/o2 input hold time t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr 0 ) t wh (cntr 0 ) t wl (cntr 0 ) t c (cntr 1 ) t wh (cntr 1 ) t wl (cntr 1 ) t c (s clk1 ) t wh (s clk1 ) t wl (s clk1 ) t su (rxd 1 s clk1 ) t h (s clk1 rxd 1 ) t c (s clk2 ) t wh (s clk2 ) t wl (s clk2 ) t su (s data2 s clk2 ) t h (s clk2 s data2 ) 2 250 100 100 500 230 230 4000 1600 1600 2000 950 950 400 200 2000 950 950 400 400 s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns note: in this time, bit 6 of the serial i/o1 control register (address 001a 16 ) is set to 1 (clock synchronous serial i/o1 is selected). when bit 6 of the serial i/o1 control register is 0 (clock asynchronous serial i/o1 is selected), the rating values are divided by 4. single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 70 switching characteristics measurement circuit diagram (gen- eral purpose) / / / measured output pin cmos output 100 pf switching characteristics (extended operating temperature version) table 28 switching characteristics (1) (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) t c (s clk1 )/2 30 t c (s clk1 )/2 30 30 t c (s clk2 )/2 30 t c (s clk2 )/2 30 0 min. typ. max. symbol parameter limits unit t wh (s clk1 ) t wl (s clk1 ) t d (s clk1 txd 1 ) t v (s clk1 txd 1 ) t r (s clk1 ) t f (s clk1 ) t wh (s clk2 ) t wl (s clk2 ) t d (s clk2 s data2 ) t v (s clk2 s data2 ) t r (s clk2 ) t f (s clk2 ) t r (cmos) t f (cmos) serial i/o1 clock output h pulse width serial i/o1 clock output l pulse width serial i/o1 output delay time serial i/o1 output valid time serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output h pulse width serial i/o2 clock output l pulse width serial i/o2 output delay time serial i/o2 output valid time serial i/o2 clock output rising time serial i/o2 clock output falling time cmos output rising time (note 1) cmos output falling time (note 1) note 1: pin x out is excluded. table 29 switching characteristics (2) (v cc = 2.4 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit 350 50 50 350 50 50 50 50 note 1: pin x out is excluded. t wh (s clk1 ) t wl (s clk1 ) t d (s clk1 t x d 1 ) t v (s clk1 t x d 1 ) t r (s clk1 ) t f (s clk1 ) t wh (s clk2 ) t wl (s clk2 ) t d (s clk2 s data2 ) t v (s clk2 s data2 ) t r (s clk2 ) t f (s clk2 ) t r (cmos) t f (cmos) serial i/o1 clock output h pulse width serial i/o1 clock output l pulse width serial i/o1 output delay time serial i/o1 output valid time serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output h pulse width serial i/o2 clock output l pulse width serial i/o2 output delay time serial i/o2 output valid time serial i/o2 clock output rising time serial i/o2 clock output falling time cmos output rising time (note 1) cmos output falling time (note 1) t c (s clk1 )/2 50 t c (s clk1 )/2 50 30 t c (s clk2 )/2 50 t c (s clk2 )/2 50 0 20 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 140 30 30 140 30 30 30 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 71 fig. 56 timing chart (extended operating temperature version) 0.2v cc t d (s clk1 -txd 1 ) t f 0.2v cc 0.8v cc 0.8v cc t r t su (rxd 1 -s clk1 )t h (s clk1 -rxd 1 ) t v (s clk1 -txd 1 ) t c (s clk1 ) t wl (s clk1 ) t wh (s clk1 ) r x d 1 (at receive) s clk1 0.2v cc t wl (x in ) 0.8v cc t wh (x in ) t c (x in ) x in 0.2v cc 0.8v cc t w (reset) reset 0.2v cc t wl (cntr 0 ) 0.8v cc t wh (cntr 0 ) t c (cntr 0 ) t x d 1 (at transmit) cntr 0 0.2v cc t wl (cntr 0 ) 0.8v cc t wh (cntr 0 ) int 0 , int 1 0.2v cc t wl (cntr 1 ) 0.8v cc t wh (cntr 1 ) t c (cntr 1 ) cntr 1 0.2v cc t d (s clk2 -s data2 ) t f 0.2v cc 0.8v cc 0.8v cc t r t su (s data2 -s clk2 )t h (s clk2 -s data2 ) t v (s clk2 -s data2 ) t c (s clk2 ) t wl (s clk2 ) t wh (s clk2 ) s data2 (at receive) s clk2 s data2 (at transmit) single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 72 electrical characteristics 3.7540group (extended operating temperature 125 ? version) applied to: m37540m2v-xxxfp/gp, m37540m4v-xxxfp/gp, m37540e8v-xxxfp/gp absolute maximum ratings (extended operating temperature 125 ? version) table 30 absolute maximum ratings 0.3 to 6.5 ( note 1 ) 0.3 to v cc + 0.3 0.3 to v cc + 0.3 0.3 to v cc + 0.3 300 ( note 2 ) 40 to 125 ( note 3 ) 65 to 150 power source voltage input voltage p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 , v ref input voltage reset, x in , cnv ss output voltage p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 , x out power dissipation operating temperature storage temperature v v v v mw c c v cc v i v i v o p d t opr t stg conditions symbol ratings unit parameter all voltages are based on v ss . output transistors are cut off. ta = 25 c notes 1: this is the rating value for the mask rom version. the rating value for the one time prom version is 0.3 to 7.0 v. 2: 200 mw for the 32p6u package product. 3: in this version, the operating temperature range and total time are limited as follows; 55 c to 85 c: within total 6000 hours, 85 c to 125 c: within total 1000 hours. single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 73 recommended operating conditions (extended operating temperature 125 ? version) table 31 recommended operating conditions (1) (v cc = 2.4 to 5.5 v, ta = ?0 to 125 ?, unless otherwise noted) 5.5 5.5 5.5 5.5 5.5 5.5 v cc v cc v cc v cc 4.0 2.4 4.0 2.4 4.0 2.4 2.0 0.8v cc 2.0 0.8v cc 0 0 0 0 min. typ. max. symbol parameter unit power source voltage (ceramic) f(x in ) = 8 mhz (high-, middle-speed mode) f(x in ) = 4 mhz (high-, middle-speed mode) f(x in ) = 4 mhz (double-speed mode) f(x in ) = 2 mhz (double-speed mode) f(x in ) = 4 mhz (high-, middle-speed mode) f(x in ) = 2 mhz (high-, middle-speed mode) 5.0 5.0 5.0 5.0 5.0 5.0 0 limits v cc v v v v v v v v v v v v v v v ma ma ma ma ma ma power source voltage analog reference voltage h input voltage p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 h input voltage (ttl input level selected) p1 0 , p1 2 , p1 3 , p3 6 , p3 7 (note 1) h input voltage reset, x in l input voltage p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 l input voltage (ttl input level selected) p1 0 , p1 2 , p1 3 , p3 6 , p3 7 (note 1) l input voltage reset, cnv ss l input voltage x in h total peak output current (note 2) p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 l total peak output current (note 2) p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 7 l total peak output current (note 2) p3 0 p3 6 h total average output current (note 2) p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 l total average output current (note 2) p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 7 l total average output current (note 2) p3 0 p3 6 note 1: vcc = 4.0 to 5.5v 2: the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an average value measured over 100 ms. the total peak current is the peak value of all the currents. 0.3v cc 0.8 0.2v cc 0.16v cc 80 80 60 40 40 30 v ss v ref v ih v ih v ih v il v il v il v il i oh(peak) i ol(peak) i ol(peak) i oh(avg) i ol(avg) i ol(avg) power source voltage (rc) single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 74 recommended operating conditions (extended operating temperature 125 ? version) (continued) table 32 recommended operating conditions (2) (v cc = 2.4 to 5.5 v, ta = ?0 to 125 ?, unless otherwise noted) h peak output current (note 1) p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 l peak output current (note 1) p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 7 l peak output current (note 1) p3 0 p3 6 h average output current (note 2) p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 l average output current (note 2) p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 7 l average output current (note 2) p3 0 p3 6 internal clock oscillation frequency (note 3) v cc = 4.0 to 5.5 v at ceramic oscillation or external clock input double-speed mode internal clock oscillation frequency (note 3) v cc = 2.4 to 5.5 v at ceramic oscillation or external clock input double-speed mode internal clock oscillation frequency (note 3) v cc = 4.0 to 5.5 v at ceramic oscillation or external clock input high-, middle-speed mode internal clock oscillation frequency (note 3) v cc = 2.4 to 5.5 v at ceramic oscillation or external clock input high-, middle-speed mode internal clock oscillation frequency (note 3) v cc = 4.0 to 5.5 v at rc oscillation high-, middle-speed mode internal clock oscillation frequency (note 3) v cc = 2.4 to 5.5 v at rc oscillation high-, middle-speed mode ma ma ma ma ma ma mhz mhz mhz mhz mhz mhz symbol parameter limits unit max. typ. min. 10 10 30 5 5 15 4 2 8 4 4 2 notes 1: the peak output current is the peak current flowing in each port. 2: the average output current i ol (avg), i oh (avg) in an average value measured over 100 ms. 3: when the oscillation frequency has a duty cycle of 50 %. i oh(peak) i ol(peak) i ol(peak) i oh(avg) i ol(avg) i ol(avg) f(x in ) single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 75 electrical characteristics (extended operating temperature 125 ? version) table 33 electrical characteristics (1) (v cc = 2.4 to 5.5 v, v ss = 0 v, ta = ?0 to 125 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit i oh = 5 ma v cc = 4.0 to 5.5 v i oh = 1.0 ma v cc = 2.4 to 5.5 v i ol = 5 ma v cc = 4.0 to 5.5 v i ol = 1.5 ma v cc = 4.0 to 5.5 v i ol = 1.0 ma v cc = 2.4 to 5.5 v i ol = 15 ma v cc = 4.0 to 5.5 v i ol = 1.5 ma v cc = 4.0 to 5.5 v i ol = 10 ma v cc = 2.4 to 5.5 v v i = v cc (pin floating. pull up transistors off ) v i = v cc v i = v cc v i = v ss (pin floating. pull up transistors off ) v i = v ss v i = v ss v i = v ss (pull up transistors on ) when clock stopped v cc = 5.0 v, ta = 25 c v cc = 5.0 v, ta = 25 c test conditions v cc 1.5 v cc 1.0 2.0 1000 62.5 h output voltage p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 (note 1) l output voltage p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 7 l output voltage p3 0 p3 6 hysteresis cntr 0 , cntr 1 , int 0 , int 1 (note 2) p0 0 p0 7 (note 3) hysteresis r x d, s clk1 , s clk2 , s data2 (note 2) hysteresis reset h input current p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 h input current reset h input current x in l input current p0 0 p0 7 , p1 0 p1 4 , p2 0 p2 7 , p3 0 p3 7 l input current reset, cnv ss l input current x in l input current p0 0 p0 7 , p3 0 p3 7 ram hold voltage ring oscillator oscillation frequency oscillation stop detection circuit detection frequency 1.5 0.3 1.0 2.0 0.3 1.0 5.0 5.0 5.0 5.0 0.5 5.5 3000 187.5 v v v v v v v v v v v a a a a a a ma v khz khz v oh v ol v ol v t+ v t v t+ v t v t+ v t i ih i ih i ih i il i il i il i il v ram r osc d osc 0.4 0.5 0.5 4.0 4.0 0.2 2000 125 notes 1: p1 1 is measured when the p1 1 /t x d 1 p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0 . 2: r x d1, s clk1 , s clk2 , s data2 , int 0 , and int 1 have hysteresises only when bits 0 to 2 of the port p1p3 control register are set to 0 (cmos level). 3: it is available only when operating key-on wake up. single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 76 electrical characteristics (extended operating temperature 125? version)(continued) table 34 electrical characteristics (2) (v cc = 2.4 to 5.5 v, v ss = 0 v, ta = ?0 to 125 ?, unless otherwise noted) min. typ. max. symbol limits unit 8.0 1.5 5.0 1000 3.2 450 1.0 50 6.5 1.2 5.0 900 3.2 450 1.0 50 ma ma ma a ma ma a ma a a ma ma ma a ma ma a ma a a i cc 5.0 0.5 2.0 350 1.6 0.2 150 0.5 0.1 3.5 0.4 2.0 300 1.6 0.2 150 0.5 0.1 high-speed mode, f(x in ) = 8 mhz output transistors off high-speed mode, f(x in ) = 2 mhz, v cc = 2.4 v output transistors off middle-speed mode, f(x in ) = 8 mhz, output transistors off ring oscillator operation mode, v cc = 5 v output transistors off f(x in ) = 8 mhz (in wit state), functions except timer 1 disabled, output transistors off f(x in ) = 2 mhz, v cc = 2.4 v (in wit state), functions except timer 1 disabled, output transistors off ring oscillator operation mode, v cc = 5v (in wit state), functions except timer 1 disabled, output transistors off increment when a-d conversion is executed f(x in ) = 8 mhz, v cc = 5 v all oscillation stopped (in stp state) output transistors off high-speed mode, f(x in ) = 8 mhz output transistors off high-speed mode, f(x in ) = 2 mhz, v cc = 2.4 v output transistors off middle-speed mode, f(x in ) = 8 mhz, output transistors off ring oscillator operation mode, v cc = 5 v output transistors off f(x in ) = 8 mhz (in wit state), functions except timer 1 disabled, output transistors off f(x in ) = 2 mhz, v cc = 2.4 v (in wit state), functions except timer 1 disabled, output transistors off ring oscillator operation mode, v cc = 5v (in wit state), functions except timer 1 disabled, output transistors off increment when a-d conversion is executed f(x in ) = 8 mhz, v cc = 5 v all oscillation stopped (in stp state) output transistors off ta = 25 c ta = 125 c test conditions one time prom version mask rom version ta = 25 c ta = 125 c single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 77 a-d converter characteristics (extended operating temperature 125 ? version) table 35 a-d converter characteristics (v cc = 2.7 to 5.5 v, v ss = 0 v, ta = ?0 to 125 ?, unless otherwise noted) resolution linearity error differential nonlinear error zero transition voltage full scale transition voltage conversion time ladder resistor reference power source input current a-d port input current resolution linearity error differential nonlinear error zero transition voltage full scale transition voltage conversion time ladder resistor reference power source input current a-d port input current min. typ. max. symbol parameter limits unit test conditions v cc = 2.7 to 5.5 v ta = 25 ? v cc = 2.7 to 5.5 v ta = 25 ? v cc = v ref = 5.12 v v cc = v ref = 3.072 v v cc = v ref = 5.12 v v cc = v ref = 3.072 v v ref = 5.0 v v ref = 3.0 v v cc = 2.7 to 5.5 v ta = 25 ? v cc = 2.7 to 5.5 v ta = 25 ? v cc = v ref = 5.12 v v cc = v ref = 3.072 v v cc = v ref = 5.12 v v cc = v ref = 3.072 v v ref = 5.0 v v ref = 3.0 v bits lsb lsb mv mv mv mv tc(x in ) k ? a a bits lsb lsb mv mv mv mv tc(x in ) k ? a a 10 ? ?.9 20 15 5125 3075 122 200 120 7.0 10 ? ?.5 35 21 5150 3090 122 200 120 7.0 v ot v fst t conv r ladder i vref i i(ad) v ot v fst t conv r ladder i vref i i(ad) 5 3 5115 3069 55 150 70 15 9 5125 3075 55 150 70 0 0 5105 3060 50 30 0 0 5105 3060 50 30 one time prom version mask rom version single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 78 timing requirements (extended operating temperature 125 ? version) table 36 timing requirements (1) (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = ?0 to 125 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit reset input l pulse width external clock input cycle time external clock input h pulse width external clock input l pulse width cntr 0 input cycle time cntr 0 , int 0 , int 1 , input h pulse width cntr 0 , int 0 , int 1 , input l pulse width cntr 1 input cycle time cntr 1 input h pulse width cntr 1 input l pulse width serial i/o1 clock input cycle time (note) serial i/o1 clock input h pulse width (note) serial i/o1 clock input l pulse width (note) serial i/o1 input set up time serial i/o1 input hold time serial i/o2 clock input cycle time serial i/o2 clock input h pulse width serial i/o2 clock input l pulse width serial i/o2 input set up time serial i/o2 input hold time t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr 0 ) t wh (cntr 0 ) t wl (cntr 0 ) t c (cntr 1 ) t wh (cntr 1 ) t wl (cntr 1 ) t c (s clk1 ) t wh (s clk1 ) t wl (s clk1 ) t su (rxd 1 s clk1 ) t h (s clk1 rxd 1 ) t c (s clk2 ) t wh (s clk2 ) t wl (s clk2 ) t su (s data2 s clk2 ) t h (s clk2 s data2 ) 2 125 50 50 200 80 80 2000 800 800 800 370 370 220 100 1000 400 400 200 200 s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns note: in this time, bit 6 of the serial i/o1 control register (address 001a 16 ) is set to 1 (clock synchronous serial i/o1 is selected). when bit 6 of the serial i/o1 control register is 0 (clock asynchronous serial i/o1 is selected), the rating values are divided by 4. table 37 timing requirements (2) (v cc = 2.4 to 5.5 v, v ss = 0 v, ta = ?0 to 125 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit reset input l pulse width external clock input cycle time external clock input h pulse width external clock input l pulse width cntr 0 input cycle time cntr 0 , int 0 , int 1 , input h pulse width cntr 0 , int 0 , int 1 , input l pulse width cntr 1 input cycle time cntr 1 input h pulse width cntr 1 input l pulse width serial i/o1 clock input cycle time (note) serial i/o1 clock input h pulse width (note) serial i/o1 clock input l pulse width (note) serial i/o1 input set up time serial i/o1 input hold time serial i/o2 clock input cycle time serial i/o2 clock input h pulse width serial i/o2 clock input l pulse width serial i/o2 input set up time serial i/o2 input hold time t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr 0 ) t wh (cntr 0 ) t wl (cntr 0 ) t c (cntr 1 ) t wh (cntr 1 ) t wl (cntr 1 ) t c (s clk1 ) t wh (s clk1 ) t wl (s clk1 ) t su (rxd 1 s clk1 ) t h (s clk1 rxd 1 ) t c (s clk2 ) t wh (s clk2 ) t wl (s clk2 ) t su (s data2 s clk2 ) t h (s clk2 s data2 ) 2 250 100 100 500 230 230 4000 1600 1600 2000 950 950 400 200 2000 950 950 400 400 s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns note: in this time, bit 6 of the serial i/o1 control register (address 001a 16 ) is set to 1 (clock synchronous serial i/o1 is selected). when bit 6 of the serial i/o1 control register is 0 (clock asynchronous serial i/o1 is selected), the rating values are divided by 4. single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 79 switching characteristics measurement circuit diagram (gen- eral purpose) / / / measured output pin cmos output 100 pf switching characteristics (extended operating temperature 125 ? version) table 38 switching characteristics (1) (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = ?0 to 125 ?, unless otherwise noted) t c (s clk1 )/2 30 t c (s clk1 )/2 30 30 t c (s clk2 )/2 30 t c (s clk2 )/2 30 0 min. typ. max. symbol parameter limits unit t wh (s clk1 ) t wl (s clk1 ) t d (s clk1 txd 1 ) t v (s clk1 txd 1 ) t r (s clk1 ) t f (s clk1 ) t wh (s clk2 ) t wl (s clk2 ) t d (s clk2 s data2 ) t v (s clk2 s data2 ) t r (s clk2 ) t f (s clk2 ) t r (cmos) t f (cmos) serial i/o1 clock output h pulse width serial i/o1 clock output l pulse width serial i/o1 output delay time serial i/o1 output valid time serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output h pulse width serial i/o2 clock output l pulse width serial i/o2 output delay time serial i/o2 output valid time serial i/o2 clock output rising time serial i/o2 clock output falling time cmos output rising time (note 1) cmos output falling time (note 1) note 1: pin x out is excluded. table 39 switching characteristics (2) (v cc = 2.4 to 5.5 v, v ss = 0 v, ta = ?0 to 125 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit 350 50 50 350 50 50 50 50 note 1: pin x out is excluded. t wh (s clk1 ) t wl (s clk1 ) t d (s clk1 t x d 1 ) t v (s clk1 t x d 1 ) t r (s clk1 ) t f (s clk1 ) t wh (s clk2 ) t wl (s clk2 ) t d (s clk2 s data2 ) t v (s clk2 s data2 ) t r (s clk2 ) t f (s clk2 ) t r (cmos) t f (cmos) serial i/o1 clock output h pulse width serial i/o1 clock output l pulse width serial i/o1 output delay time serial i/o1 output valid time serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output h pulse width serial i/o2 clock output l pulse width serial i/o2 output delay time serial i/o2 output valid time serial i/o2 clock output rising time serial i/o2 clock output falling time cmos output rising time (note 1) cmos output falling time (note 1) t c (s clk1 )/2 50 t c (s clk1 )/2 50 30 t c (s clk2 )/2 50 t c (s clk2 )/2 50 0 20 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 140 30 30 140 30 30 30 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 80 fig. 57 timing chart (extended operating temperature 125 ? version) 0.2v cc t d (s clk1 -txd 1 ) t f 0.2v cc 0.8v cc 0.8v cc t r t su (rxd 1 -s clk1 )t h (s clk1 -rxd 1 ) t v (s clk1 -txd 1 ) t c (s clk1 ) t wl (s clk1 ) t wh (s clk1 ) r x d 1 (at receive) s clk1 0.2v cc t wl (x in ) 0.8v cc t wh (x in ) t c (x in ) x in 0.2v cc 0.8v cc t w (reset) reset 0.2v cc t wl (cntr 0 ) 0.8v cc t wh (cntr 0 ) t c (cntr 0 ) t x d 1 (at transmit) cntr 0 0.2v cc t wl (cntr 0 ) 0.8v cc t wh (cntr 0 ) int 0 , int 1 0.2v cc t wl (cntr 1 ) 0.8v cc t wh (cntr 1 ) t c (cntr 1 ) cntr 1 0.2v cc t d (s clk2 -s data2 ) t f 0.2v cc 0.8v cc 0.8v cc t r t su (s data2 -s clk2 )t h (s clk2 -s data2 ) t v (s clk2 -s data2 ) t c (s clk2 ) t wl (s clk2 ) t wh (s clk2 ) s data2 (at receive) s clk2 s data2 (at transmit) single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 81 package outline lqfp32-p-0707-0.80 weight(g) jedec code eiaj package code lead material cu alloy 32p6u-a plastic 32pin 7 ? 7mm body lqfp 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 i 2 1.0 m d m e 10 0 0.1 1.0 0.7 0.2 0.5 0.3 0.8 6.9 7.0 7.1 6.9 7.0 7.1 8.8 9.0 9.2 8.8 9.0 9.2 0.175 0.125 0.105 0.45 0.37 0.32 1.4 0 1.7 e lp 0.45 0.6 0.5 7.4 7.4 0.25 0.75 x a3 recommended mount pad detail f a e h e h d d 1 8 24 17 25 32 16 9 m d b 2 m e e f e y b x m a 1 a 2 l l 1 lp a3 c i 2 mmp ssop36-p-450-0.80 weight(g) e jedec code 0.53 eiaj package code lead material alloy 42 36p2r-a plastic 36pin 450mil ssop symbol min nom max a a 2 b c d e l l 1 y dimension in millimeters h e a 1 i 2 e e .35 0 .05 0 .13 0 .8 14 .2 8 e .63 11 .3 0 e e e .27 1 e e .0 2 .4 0 .15 0 .0 15 .4 8 .8 0 .93 11 .5 0 .765 1 e .43 11 e e .4 2 e .5 0 .2 0 .2 15 .6 8 e .23 12 .7 0 e .15 0 e b 2 e.5 0e e 0 single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers 82 sdip32-p-400-1.78 weight(g) e 2.2 jedec code eiaj package code lead material alloy 42/cu alloy 32p4b plastic 32pin 400mil sdip symbol min nom max a a 2 b b 1 b 2 c e d l dimension in millimeters a 1 0.51 ee e 3.8 e 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 27.8 28.0 28.2 8.75 8.9 9.05 e 1.778 e e 10.16 e 3.0 ee 0 15 5.08 e e 1 32 17 16 1 e c e 1 a 2 a 1 b 2 b b 1 e la seating plane d mmp single-chip 8-bit cmos microcomputer 7540 group mitsubishi microcomputers ? 2000 mitsubishi electric corp. ki-0011 printed in japan (rod) ii new publication, effective nov. 2000 specifications subject to change without notice. notes regarding these materials these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product be st suited to the customer s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents info rmation on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that c ustomers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assu mes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubish i semiconductor home page (http://www.mitsubishichips.com). when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used unde r circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herei n for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these ma terials. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a licens e from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further detail s on these materials or the products contained therein. keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with a ppropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. head office: 2-2-3, marunouchi, chiyoda-ku, tokyo 100-8310, japan rev. rev. no. date 1.0 first edition 991122 2.0 page 1: 010108 features ?the minimum instruction execution time revised; 0.34 s (at 6 mhz oscillation frequency, double-speed mode for the shortest instruction) ?power source voltage added; x in oscillation frequency at ceramic oscillation , in high-speed mode at 6 mhz.......................................4.5 to 5.5 v ?power dissipation revised; mask rom version........................22.5 mw (standard) one time prom version..............30 mw (standard) pin configuration fig. 1 revised; package type 32p6 u-a, product name ?37540m4t-xxxgp?added page 2: fig. 2 revised; product name ?37540m4t-xxxfp?added page 3: fig. 4 m37540rss pin configuration (42s1m) added page 4: fig. 5 functional block diagram revised; package type 32p6 u page 7: pin description revised; notes 1 to 3 added page 8: package type revised; 32p6 u-a.....0.8 mm-pitch plastic molded lqfp 36p2r-a.....0.8 mm-pitch plastic molded ssop table 2 revised; package type 32p6 u-a pages 9 to 11: structure of cpu added page 12: fig. 11 initial value added, fig. 12 description revised page 16: table 5 non-port function of port p0 revised, notes 2 and 3 added page 17: fig. 17 port p0 revised page 18: fig. 18 note added page 20: fig. 20 initial values added, interrupt enable bit of icon1; note added page 21: fig. 21 port p0 0 key-on wakeup selection bit added revision description list 7540 group data sheet (1/4) revision description rev. rev. no. date 2.0 (continued) 010108 pages 22 to 30: description of timers revised all page 31: fig. 25 to fig. 27 initial values added page 33: fig. 29 reference of figure revised fig. 50, 51 page 36: description of sio1sts revised; ?ll bits? ?its 0 to 6 description of uartcon revised; ?1 2 /s clk1 ?pin eliminated page 37: fig. 34 initial value added page 38: fig. 35 initial value added page 39: fig. 37 note revised page 40: fig. 38 initial value added page 41: fig. 42 initial value added page 42: description in the case of 6 mhz added page 43: fig. 45 contents of (7), (8) revised page 45: fig. 49 functions of b1 and b7 revised, initial value added page 46: fig. 50 a resistor of x out pin eliminated page 47: description of oscillation stop detection circuit added, fig. 52 revised page 48: notes on ports revised pages 50 to 68: electrical characteristics revised all page 69: package type revised; 32p6 u-a 3.0 all pages: the following is eliminated; 020610 ?reliminary notice: this is not a final specification. some parametric limits are subject to change. page 1: ?memory size rom/ram size revised, ?operating temperature range 125 ? version added, and note revised page 2: fig. 1 and fig. 2 product name revised page 3: fig. 3 product name revised page 7: table 1 x in , x out functional description added, note 1 125 ? version added page 8: memory size rom/ram size, package description, and fig. 8 revised page 9: table 2 revised page 14: fig. 13 rom/ram area added revision description list 7540 group data sheet (2/4) revision description (3/4) revision description list 7540 group data sheet revision description rev. rev. no. date 3.0 (continued) 020610 page 19: fig. 18 (9) port p1 4 revised page 20: note revised page 23: timer 1 ?rescaler 1 counts the signal which is the oscillation frequency divided by 16. (1) timer mode ?imer a counts the oscillation frequency divided by 16. page 24: timer x ?imer x can can be selected in one of 4 operating modes by setting the timer x operating mode bits of the timer x mode register. (1) timer mode ?rescaler x counts the count source selected by the timer x count source selection bits. page 26: timer y ?imer y can can be selected in one of 4 operating modes by setting the timer y operating mode bits of the timer y mode register. (1) timer mode ?rescaler y counts the count source selected by the timer y count source selection bits. page 27: note on reading timer added. page 28: timer z ?imer z can can be selected in one of 4 operating modes by setting the timer z operating mode bits of the timer z mode register. (1) timer mode ?rescaler z counts the count source selected by the timer z count source selection bits. page 30: note on reading timer added. page 36: note on serial i/o added. page 44: clock generating circuit the following description added. (1) ring oscillator operation, (2) ceramic resonator, (3) rc oscillation, and (4) external clock fig. 46 resistor and note added, fig. 47 note added, and fig. 49 added. page 45: oscillation stop detection circuit note added. page 46: fig. 51 and fig. 52 revised. page 47: fig. 53 note 4 added. pages 48 to 50: notes revised page 51: data required for mask orders revised data required for rom programming orders added (4/4) revision description list 7540 group data sheet revision description rev. rev. no. date 3.0 (continued) 020610 page 52: product name added, table 8 note revised. page 57: table 13 ladder resistor value revised, layout revised. page 63: product name added, table 20 note revised. page 67: table 24 characteristics for one time prom version added. mask rom version; ? cc = 5 v?eliminated from the following test condition. f(x in ) = 6 mhz f(x in ) = 8mhz, middle-speed mode page 68: table 25 ladder resistor value revised, layout revised. page 72 to 80: extended operating temperature 125 ? version added. 3.1 page 57: table 13, page 68: table 25 and page 77: table 35 020701 error of the ladder resistor in a-d converter characteristics corrected. as usual, (rev.2.0 or before), the value is not changed from typical 55 k ? . |
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